Title of Presentation：A NBTI Reliability Framework from Atoms to Processors
Time：13:30, 24th October(Wednesday) 2018
Venue：Room 108, Engineering Building 4
In this talk a NBTI (Negative Bias Temperature Instability) reliability framework will be described that can estimate the impact of gate stack processes (atoms) and MOSFET architectures on circuit reliability. A BTI analysis tool will be presented that can analyse experimental data across various technologies and processes. TCAD implementation of the framework will be shown to study FinFET scaling and GAA NSFET architectures having different channel materials and check quantum confinement and strain effects on NBTI. A compact model that can handle circuit degradation under arbitrary gate activity will be discussed, with some examples of circuit degradation under effective workload versus worst case DC cases. A simulation flow will be presented to link device and RO degradation to that of processors, which includes detailed characterization of standard cells under NBTI. Finally, the statistical aspect of SRAM variability and variable reliability will be presented.