Orbit

Kuan-Neng Chen
  • Name : Kuan-Neng Chen
  • Job Title : Professor
  • Email : knchen@mail.nctu.edu.tw
  • Office Tel No. : 03-5712121 ext. 31558
  • Research Expertise :
    Three-Dimensional Integrated Circuits (3D IC), Wafer Bonding Technology, Phase-Change Materials and Devices, Nano-scale materials and devices
  • Autobiography :  
Current Position
Professor, Department of Electronics Engineering, National Chiao Tung University
Associate Dean, International College of Semiconductor Technology, National Chiao Tung University
Adjunct Research Staff Member, National Chip Implementation Center (CIC)
Consultant, Industrial Technology and Research Institute (ITRI) 
Education
MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Cambridge, MA
Ph.D. in Electrical Engineering and Computer Science
 
MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Cambridge, MA
Master of Science in Materials Science and Engineering
Professional Experience   
  1. Vice Dean, International College of Semiconductor Technology, National Chiao Tung University, 2015 – now.
  2. Professor, Department of Electronics Engineering, National Chiao Tung University, 2012 – now.
  3. Consultant, Industrial Technology and Research Institute (ITRI), 2009 – now.
  4. Adjunct Research Staff Member, National Chip Implementation Center, 2013 - now.
  5. Visiting Scientist, Massachusetts Institute of Technology, 2015.
  6. Adjunct Associate Research Staff Member, National Chip Implementation Center, 2012.
  7. Deputy Director, ASE-NCTU R&D Center, 2011 – 2013.
  8. Visiting Professor, The University of British Columbia, Vancouver, BC, Canada, 2011.
  9. Academic Visitor, IBM T. J. Watson Research Center, 2010.
  10. Visiting Researcher, Nanyang Technological University, Singapore, 2009.
  11. Associate Professor, Department of Electronics Engineering, National Chiao Tung University, 2009 – 2012.
  12. Research Staff Member / Project Leader, IBM T. J. Watson Research Center, 2005 – 2009.
Professional Activities
 Editor
  1. Guest Editor, “Materials Challenges in Three-Dimensional Integrated Circuits”, MRS Bulletin, 40(3), Mar. 2015.
  2. Editor, Electronics Spectrum, 2011 – 2013.
  Executive Committee
  1. Director, Electronics Devices and Materials Association, 2014 – now.
  2. Secretary General, Electronics Devices and Materials Association, 2011 – 2014.
  3. Technical Program Co-Chair, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2015
  4. Tutorial Chair, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2015
  5. Co-Chair of Subprogram Committee, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2015
  6. Program Chair, IEEE International Symposium on Next-Generation Electronics (ISNE), 2014.
  7. Vice Chair of Subprogram Committee, IEEE Solid State Devices and Materials Conference (SSDM), 2013 – now.
 Technical Program Committee/Organizing Committee/Program Committee
  1. IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2017.
  2. IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 – now.
  3. IEEE Solid State Devices and Materials Conference (SSDM), 2012 – now.
  4. IEEE International 3D System Integration Conference (3DIC), 2011 – now.
  5. IMAPS International Conference and Exhibition on Device Packaging, 2008 – now.
  6. IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 – now.
  7. IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015 – now.
  8. IEEE International Symposium on Next-Generation Electronics (ISNE), 2014.
  9. International Symposium on Dry Process (DPS), 2010 – now.
  10. Taiwan ESD and Reliability Conference (TESDC), 2013 – now.
  11. IEEE International Nano Electronic Conference (INEC), 2011.
  12. International Electron Devices and Materials Symposium (IEDMS), 2010, 2013 – now.
 Session Chair/Forum Chair
  1. China Semiconductor Technology International Conference, Shanghai, China, Mar 13-14, 2016.
  2. IEEE Solid State Devices and Materials Conference (SSDM), 2012, 2013, 2015.
  3. IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr. 2015.
  4. IEEE International Symposium on Next-Generation Electronics (ISNE), 2014.
  5. IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Oct 2012.
  6. International Electron Devices and Materials Symposium (IEDMS), 2010, 2013, 2014.
  7. 3D-IC Technology Forum, The Electronics Devices and Materials Association, Hsinchu, Taiwan, Dec 18, 2009.
  8. IMAPS International Conference and Exhibition on Device Packaging, Scottsdale AZ, Mar 22, 2007.
Panel Member
  1. 3D Panel Session: Roadmap of 3D Integration and Packaging, IMAPS International Conference and Exhibition on Device Packaging, Scottsdale AZ, Mar 21, 2007.
 Government/Institute Review Committee
  1. Intelligent Electronics Institute, Ministry of Economic Affairs, 2011 – now.
  2. Industrial Development Bureau, Ministry of Economic Affairs, 2011 – now.
  3. Naitonal Nano Device Laboratories, 2014 – now.
  4. Institute for Information Industry, 2012 – now.
  5. Industrial Research and Technology Institute, 2010 – now.
  6. Hsinchu Science Based Park Bureau, Ministry of Science and Technology, 2009 – now.
Honors, Awards, Scholarships
  1. EECS Outstanding Young Scholar Award, NCTU, Jan 2016.
  2. Distinguished Faculty Award, NCTU, every year since 2011.
  3. Excellent Teaching Award, College of EE, NCTU, Jun 2015.
  4. Outstanding Electrical Engineering Professor Award, The Chinese Institute of Electrical Engineering (CICC), Dec. 2014.
  5. EDMA Outstanding Service Award, Nov. 2014.
  6. NCTU Excellent Academic Advisor Award, 2013, 2015.
  7. Outstanding Youth Electrical Engineer Award, The Chinese Institute of Electrical Engineering (CICC), Dec. 2012.
  8. NCTU Outstanding Industry-Academia Cooperation Achievement Award, 2014.
  9. NCTU Outstanding Industry-Academia Cooperation Achievement Award, 2012.
  10. NCTU Outstanding Industry-Academia Cooperation Achievement Award, 2011.
  11. EDMA Outstanding Youth Award, Nov. 2010.
  12. Adventech Young Professor Award, 2010 – 2012.
  13. LAM Best Master Thesis Award, May 2016.
  14. CICC Best Youth Paper Award, Dec 2015.
  15. IMPACT-EMAP Best Paper Award, “Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle”, Oct. 2014.
  16. IMPACT-EMAP Best Paper Award, “Low-temperature direct copper-to-copper bonding enabled by creep on highly (111)-oriented Cu surfaces”, Oct. 2014.
  17. LAM Best Master Thesis Award, Nov 2013.
  18. CICC Best Youth Paper Award, Dec 2013.
  19. LAM Best Bachelor Report Award, Nov 2012.
  20. LAM Best Master Thesis Award, Nov 2012.
  21. LAM Best Bachelor Report Award, Nov 2011.
  22. IBM Invention Achievement Award, Aug 2008.
  23. IBM Invention Achievement Award, Dec 2007.
  24. IBM Invention Achievement Award, Sep 2007.
  25. IBM Invention Achievement Award, May 2007.
  26. IBM Invention Achievement Award, Dec 2006.
  27. Phi Tau Phi Scholastic Honor Society  
Press Conference/Newspaper Article/Magazine Interview
  1. Press Conference, “交大研發第五代高階電子封裝技術 低溫(150oC)及低壓下之銅-銅直接接合”, June 3, 2015.
(http://www.appledaily.com.tw/realtimenews/article/new/20150603/621876/ )
(http://www.chinatimes.com/realtimenews/20150603002959-260412)
(http://nctunews.nctu.edu.tw/index.php/component/k2/item/913-150-oc)
  1. UST Scientific Knowledge Column, Taiwan News, “Moore, More and Much More”, July 9, 2013.
(http://www.taiwannews.com.tw/etn/news_content.php?id=22530840 )
  1. Press Conference, “Opening of ASE-NCTU Research Center”, May 23, 2011.
(http://www.pac.nctu.edu.tw/News/news_more.php?id=452)
  1. Magazine Interview, “Taiwanese Focus on 3D IC”, Semiconductor International, Nov 2009.
(http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/25466-Taiwanese_Focus_on_3D_IC.php)
  1. Magazine Interview, “Phase-Change Materials Could Boost Reconfigurable Chips”, IEEE Spectrum, Jan 2008.
(http://www.spectrum.ieee.org/jan08/5949)
  1. Magazine Interview, “Cover Story: 3D Structure Helps Moore's Law,” Nikkei Electronics, vol. 943, pp. 82-88, Jan.15 2007.  
Publication List
Book (2)
  1. 鄭晃忠, 陳冠能,“電子材料導論”, ISBN 978-986-412-927-0, 高立圖書, Mar 2013.
  2. Chuan Seng Tan, Kuan-Neng Chen, Steven J. Koester, “3D Integration for VLSI Systems”, ISBN 978-9-814-30381-1, Pan Stanford, Sep 2011.
 Book Chapter (5)
  1. 柯正達,陳裕華,陳冠能,“第五章 先進封裝電子材料”,電子材料導論,ISBN 978-986-412-927-0, 高立圖書, Mar 2013.
  2. Kuan-Neng Chen, Hsiang-Lan Lung, Yu Zhu, Huai-Yu Cheng, and Frederick T. Chen, “Phase Change Materials: Research Developments and Device Applications”, in Nonvalotile Memories: Materials, Devices and Applications, American Scientific Publisher, ISBN 978-1588832504, Mar. 2012.
  3. Kuan-Neng Chen, and Chuan Seng Tan, “Chapter 9 Thermo-Compression Cu-Cu Bonding of Blanket and Patterned Wafers”, in Handbook of Wafer Bonding, Wiley VCH, ISBN 9783527326464, Jan 2012.
  4. 陳冠能, 陳裕華, 鄭裕庭,“第十三章 三維積體電路製程”,新世代積體電路製程, ISBN 978-957-483-671-0, 東華書局, Sep 2011.
  5. Kuan-Neng Chen, Chuan Seng Tan, Andy Fan, and L Rafael Reif, “Chapter 6 Cu wafer bonding for 3D-ICs application”, in Wafer Level 3-D ICs Process Technology, ISBN 978-0-387-76532-7, Springer, Sep 2008.
 Journal (80)  Invited(7)
  1. Shih-Wei Lee, Jian-Yu Shih, Kuo-Hua Chen, Chi-Tsung Chiu, and Kuan-Neng Chen, “Polymer-Based Liner TSV Fabrication Scheme and Its Resistance Variation”, To be published in Journal of Nanoscience and Nanotechnology.
  2. Yu-Chen Hu, and Kuan-Neng Chen, “A Novel Bonding Approach and Its Electrical Performance for Flexible Substrate Integration,” IEEE Journal of the Electron Devices Society, 4(4), pp. 185-188, Jul. 2016.
  3. Yen-Jun Huang, Yen-Hui Hsieh, Jian-Yu Shih, Han-Chun Chen, Jihperng Leu, and Kuan-Neng Chen, “Adhesion Property Between Cu, Ti Metal and SU-8, AZ 4620 Polymer Dielectric,” Journal of Nanoscience and Nanotechnology, 16(7), pp. 7546-7550, Jul. 2016.
  4. Yu-Chen Hu, Chun-Pin Lin, Yao-Jen Chang, Nien-Shyang Chang, Ming-Hwa Sheu, Chi-Shi Chen, and Kuan-Neng Chen, “A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electro-less Plating on Chips with Advanced Technology Node,” IEEE Transactions​ on Electron Devices, 62(12), pp. 4148-4153, Dec. 2015.
  5. Yan-Pin Huang, Yu-San Chien, Ruoh-Ning Tzeng, and Kuan-Neng Chen, “Demonstration and Electrical Performance of Cu–Cu Bonding at 150 °C With Pd Passivation,” IEEE Transactions​ on Electron Devices, 62(8), pp. 2587-2592, Aug. 2015.
  6. Yao-Jen Chang, Cheng-Ta Ko, Tsung-Han Yu, Yu-Sheng Hsieh, and Kuan-Neng Chen, “Modeling and Characterization of TSV Capacitor and Stable Low Capacitance Implementation for Wide-I/O Application”, IEEE Transactions on Device and Materials Reliability, 15(2), pp. 129-135, Jun. 2015.
  7. Chien-Min Liu, Han-Wen Lin, Yi-Sa Huang, Yi-Cheng Chu, Chih Chen, Dian-Rong Lyu, Kuan-Neng Chen, and King-Ning Tu, “Low-temperature Direct Copper-to-Copper Bonding Enabled by Creep on (111) Surfaces of Nanotwinned Cu”, Scientific Reports, 5, 9734, May 2015.
  8. [Invited Paper] Chih Chen, Doug Yu, and Kuan-Neng Chen, “Vertical Interconnects of Microbumps in 3D Integration”, MRS Bulletin, 40(3), pp. 257-263, Mar. 2015.
  9. Kuan-Neng Chen, and King-Ning Tu, “Materials Challenges in Three-Dimensional Integrated Circuits”, MRS Bulletin, 40(3), pp. 219-222, Mar. 2015.
  10. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, Chung-Lun Lo, Chi-Chung Chang, and Kuan-Neng Chen, “Device Characteristics of TSV-Based Piezoelectric Resonator with Load Capacitance and Static Capacitance Modification,” IEEE Transactions​ on Electron Devices, 62(3), pp. 927-933, Mar. 2015.
  11. Chih-Wei Chang, Lei-Chun Chou, Po-Tsang Huang, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Jin-Chern Chiou, “A Double-Sided, Single-Chip Integration Scheme Using Through-Silicon-Via for Neural Sensing Applications,” Biomedical Microdevices, 17(1), 11, Feb. 2015.
  12. Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, and Ho-Ming Tong, “2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications,” IEEE Transactio​ns on Biomedical Circuits and Systems, 8(6), pp. 810-823, Dec. 2014,
  13. Yao-Jen Chang, Yu-Sheng Hsieh, and Kuan-Neng Chen, “Submicron Cu/Sn Bonding Technology with Transient Ni Diffusion Buffer Layer for 3DIC Application”, IEEE Electron Device Letters, 35(11), pp. 118-120, Nov. 2014.
  14. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, Chung-Lun Lo, Chi-Chung Chang and Kuan-Neng Chen, “Quartz Resonator Assembling with TSV Interposer Using Polymer Sealing or Metal Bonding,” Nanoscale Research Letters, 9, pp. 541-548, Oct. 2014.
  15. Jian-Yu Shih, Wen-Chun Huang, Cheng-Ta Ko, Zheng Yang, Sheng-Hsiang Hu, Jih-Perng Leu, Keng C. Chou, and Kuan-Neng Chen, “Adhesion Investigation between Metal and Benzocyclobutene (BCB) Polymer Dielectric Materials in 3-D Integration Applications,” IEEE Transactions on Device and Materials Reliability, 14(3), pp. 914-920, Sep. 2014.
  16. Wan-Lin Tsai, Kuang-Yu Wang, Yao-Jen Chang, Yu-Ren Li, Po-Yu Yang, Kuan-Neng Chen, and Huang-Chung Cheng, “Conductivity enhancement of multiwalled carbon nanotube thin film via thermal compression method,” Nanoscale Research Letters, 9, pp. 451-456, Aug. 2014.
  17. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, and Kuan-Neng Chen, “Motional Resistance Issue of TSV-Based Resonator Device and Its Improvement with a Concave Cu TSV Structural Design,” IEEE Electron Device Letters, 35(8), pp. 865-867, Aug. 2014.
  18. Cheng-Ta Ko, Zhi-Cheng Hsiao, Hsiang-Hung Chang, Dian-Rong Lyu, Chao-Kai Hsu, Huan-Chun Fu, Chun-Hsien Chien, Wei-Chung Lo, and Kuan-Neng Chen, “A novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices,” IEEE Transactions on Device and Materials Reliability, 14(2), pp. 715-720, Jun. 2014.
  19. Chien-Min Liu, Han-wen Lin, Yi-Cheng Chu, Chih Chen, Dian-Rong Lyu, Kuan-Neng Chen, and K. N. Tu, “Low-temperature direct copper-to-copper bonding enabled by creep on highly (111)-oriented Cu surfaces,” Scripta Materialia, 78-79, pp. 65-68, May 2014.
  20. Lei-Chun Chou, Chih-Wei Chang, Po-Tsang Huang, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuan-Neng Chen, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong, “A New Fabrication Process for TSV-based Bio-signal Packaging,” Storage Management Solutions, 3, pp. 157-168, May 2014.
  21. Yu-San Chien, Yan-Pin Huang, Ruoh-Ning Tzeng, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, “Low-Temperature Bonded Cu/In Interconnect with High Thermal Stability for 3-D Integration,” IEEE Transactions on Electron Devices, 61(4), pp. 1131-1136, Apr. 2014.
  22. Li-Min Kuo, Yi-Chia Chou, Kuan-Neng Chen, Chien-Chia Lu, and Shuchi Chao, “A precise pH microsensor using RF-sputtering IrO2 and Ta2O5 films on Pt-electrode,” Sensors and Actuators B: Chemical, 193, pp. 687-691, Mar. 2014.
  23. Lei-Chun Chou, Shih-Wei Lee, Po-Tsang Huang, Chih-Wei Chang, Cheng-Hao Chiang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, “A TSV-Based Bio-Signal Package with μ-probe Array,” IEEE Electron Device Letters, 35(2), pp. 256-258, Feb. 2014.
  24. Yan-Pin Huang, Yu-San Chien, Ruoh-Ning Tzeng, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Ho-Ming Tong, and Kuan-Neng Chen, “Novel Cu-to-Cu Bonding with Ti Passivation at 180C in 3D Integration”, IEEE Electron Device Letters, 34(12), pp. 1551-1553, Dec. 2013.
  25. Hsiao-Yu Chen, Sheng-Yao Hsu, and Kuan-Neng Chen, “Electrical Performance and Reliability Investigation of Co-sputtered Cu/Ti Bonded Interconnects”, IEEE Transactions on Electron Devices, 60(10), pp. 3521-3526, Oct. 2013.
  26. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, Yu-Chen Hu, Chung-Lun Lo, Chi-Chung Chang, and Kuan-Neng Chen, “Advanced TSV-Based Crystal Resonator Devices Using 3-D Integration Scheme with Hermetic Sealing”, IEEE Electron Device Letters, 34(8), pp. 1041-1043, Aug. 2013.
  27. Cheng-Hao Chiang, Li-Min Kuo, Yu-Chen Hu, Wen-Chun Huang, Cheng-Ta Ko, and Kuan-Neng Chen, “Sealing Bump with Bottom-up Cu TSV Plating Fabrication in 3-D Integration Scheme”, IEEE Electron Device Letters, 34(5), pp. 671-673, May 2013.
  28. Yao-Jen Chang, Cheng-Ta Ko, Tsung-Han Yu, Cheng-Hao Chiang, and Kuan-Neng Chen, “Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding”, IEEE Electron Device Letters, 34(3), pp. 435-437, Mar. 2013.
  29. Li-Min Kuo, Kuan-Neng Chen, Yi-Lin Chuang, and Shuchi Chao, “Flexible pH-Sensing Structure using WO3/IrO2 Junction with Al2O3 Encapsulation Layer”, ECS Solid-State Letters, 2(3), pp. 28-30, 2013.
  30. Yao-Jen Chang, Cheng-Ta Ko, and Kuan-Neng Chen, “Electrical and Reliability Investigation of Cu TSVs with Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme”, IEEE Electron Device Letters, 34(1), pp. 102-104, Jan. 2013.
  31. Yew Heng Tan, Kwang Sing Yew, Kwang Hong Lee, Yao-Jen Chang, Kuan-Neng Chen, Diing Shenp Ang, Eugene A. Fitzgerald, and Chuan Seng Tan “Al2O3 Interface Engineering of Germanium Epitaxial Layer Grown Directly on Silicon”, IEEE Transactions on Electron Devices, 60(1), pp. 56-62, Jan. 2013.
  32. [Invited Paper] Cheng-Ta Ko, and Kuan-Neng Chen, “Reliability of Key Technologies in 3D Integration”, Microelectronics Reliability, 53(1), pp. 7-16, Jan. 2013.
  33. Cheng-Hsien Lu, Chuan-An Cheng, Chia-Hua Ho, and Kuan-Neng Chen, “Effects of Bonding Technology and Thinning Process in Three-Dimensional Integration on Device Characteristics”, Journal of Nanoscience and Nanotechnology, 12, pp. 8050-8054, Oct. 2012.
  34. Sheng-Yao Hsu, Hsiao-Yu Chen, and Kuan-Neng Chen, “Co-sputtered Cu/Ti Bonded Interconnects with a Self-formed Adhesion Layer for 3D Integration Applications”, IEEE Electron Device Letters, 33(7), pp. 1048-1050, July 2012.
  35. Cheng-Ta Ko, Zhi-Cheng Hsiao, Yao-Jen Chang, Peng-Shu Chen, Yu-Jiau Hwang, Huan-Chun Fu, Jui-Hsiung Huang, Chia-Wen Chiang, Shyh-Shyuan Sheu, Yu-Hua Chen, Wei-Chung Lo, and Kuan-Neng Chen, “A Wafer-level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Bonding for 3D Memory Application”, IEEE Transactions on Device and Materials Reliability, 12(2), pp.209-216, June 2012.
  36. S. Y. Hsu, H. Y. Chen and K. N. Chen, “Diffusion of Co-Sputtered Metals as Bonding Materials for 3D Interconnects during Thermal Treatments,” Journal of Nanoscience and Nanotechnology, 12, pp.2467-2471, Mar 2012.
  37. Kuan-Neng Chen, Cheng-Ta Ko, Zhi-Cheng Hsiao, Huan-Chun Fu, and Wei-Chung Lo, “Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration,” Journal of Nanoscience and Nanotechnology, 12, pp.1821-1828, Mar 2012.
  38. S. L. Lin, W. C. Huang, C. T. Ko, and K. N. Chen, “BCB-to-Oxide Bonding Technology for 3D Integration”, Microelectronics Reliability, 52, pp. 352-355, Feb 2012.
  39. [Invited Paper] Ya-Sheng Tang, Yao-Jen Chang, and Kaun-Neng Chen, “Wafer-Level Cu-Cu Bonding Technology”, Microelectronics Reliability, 52, pp. 312-320, Feb 2012.
  40. [Invited Paper] Cheng-Ta Ko, and Kaun-Neng Chen, “Low Temperature Bonding Technology for 3D Integration”, Microelectronics Reliability, 52, pp. 302-311, Feb 2012.
  41. Ming-Fang Lai, Shih-Wei Li, Jian-Yu Shih, and Kuan-Neng Chen, “Wafer-Level Three-Dimensional Integrated Circuits (3D IC): Schemes and Key Technologies”, Microelectronic Engineering, 88, pp. 3282-3286, Nov 2011.
  42. K. N. Chen, C. A. Cheng, W. C. Huang and C. T. Ko, “Bonding Temperature Optimization and Property Evolution of SU-8 Material in Metal/Adhesive Hybrid Wafer Bonding,” Journal of Nanoscience and Nanotechnology, 11, pp. 6969-6972, Aug 2011.
  43. Sang Hwui Lee, Kuan-Neng Chen, and Jian-Qiang Lu, “Wafer-to-wafer Alignment for 3D Integration: An Review”, IEEE Journal of Microelectromechanical Systems. 20(4), pp. 885-898, Aug 2011.
  44. Kuan-Neng Chen, Zheng Xu, and Jiang-Qiang Lu, “Electrical Performance and Alignment Investigation of Wafer-level Cu-oxide Hybrid Bonding,” IEEE Electron Device Letters, 32(8), pp. 1119-1121, Aug 2011.
  45. K.N. Chen, A. M. Young, S. H. Lee, and J. -Q. Lu, “Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integration,” Journal of Nanoscience and Nanotechnology, 11, pp. 5143-5147, June. 2011.
  46.  [Invited Paper] Kuan-Neng Chen, and Chuan Seng Tan, “Integration Schemes and Enabling Technologies for Three-Dimensional Integrated Circuits (3D IC)”, IET Computers and Digital Techniques, 5(3), pp. 160-168, May 2011.
  47. K. N. Chen, C. K. Tsang, W. W. Wu, S. H. Lee, and J. Q. Lu, “Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration Applications”, Journal of Nanoscience and Nanotechnology, 11, pp. 3336-3339, Apr. 2011.
  48. W. W. Wu, K. C. Lu, K. N. Chen, P. H. Yeh, C. W. Wang, Y. C. Lin, and Y. Huang “Controlled large strain of Si in the NiSi/Si/NiSi nanowire heterostructure”, Applied Physics Letters, 97, pp 203110-1 – 203110-3, Dec. 2010.
  49. K.N. Chen, Y. Zhu, W.W. Wu, and R. Reif, “Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes”, Journal of Electronic Materials. 39(12), pp. 2605-2610, Dec. 2010.
  50. Kuan-Neng Chen, and John C. Arnold, “Wafer-level Self-aligned Nano Tubular Structures and Templates for Device Applications“, Journal of Nanoscience and Nanotechnology, 10, pp. 8145-8150, Dec. 2010.
  51. W.W. Wu, C. W. Wang, K.N. Chen, S. L. Cheng, and S. W. Lee, “Enhanced growth of low-resistivity titanium silicides on epitaxial Si0.7Ge0.3 on (001)Si with a sacrificial amorphous Si interlayer”, Thin Solid Films, 518, pp. 7279-7282, Oct. 2010.
  52. [Invited Paper] Cheng-Ta Ko and Kuan-Neng Chen, “Wafer Level Bonding/Stacking Technology for 3D Integration”, Microelectronics Reliability, 50 (4), pp. 481-488, April 2010.
  53. Kuan-Neng Chen, and Lia Krusin-Elbaum, “The fabrication of a programmable via using phase-change material in CMOS-compatible technology“, Nanotechnology, 21 (13), 134001, April 2010.
  54. K. N. Chen, C. Cabral Jr. and L. Krusin-Elbaum, “Thermal stress effects of Ge2Sb2Te5 phase change material: Irreversible modification with Ti adhesion layers and segregation of Te”, Microelectronic Engineering, 85, pp 2346-2349, Dec. 2008.
  55. S. J. Koester, A. M. Young, R. R. Yu, S. Purushothama, K.-N. Chen, D. C. La Tulipe, N. Rana, L. Shi, Matt R. Wordeman, and E. J. Sprogis, “Wafer-Level 3D Integration Technology”,  IBM Journal of Research and Development, 52 (6), pp 583-597, Jul. 2008.
  56. K. N. Chen, L. Krusin-Elbaum, D. Newns, B. Elmegreen, R. Cheek, N. Rana, A. Young, S. Koester, and C. Lam, “Programmable Via Using Indirectly Heated Phase-Change Switch for Reconfigurable Applications”, IEEE Electron Device Letters, 29, pp 131-133, Jan. 2008.
  57. L. Krusin-Elbaum, C. Cabral Jr., K. N. Chen, M. Copel, D. W. Abraham, K. B. Reuter, S. M. Rossnagel, J. Bruley, and V. Deline, “Evidence for segregation of Te in Ge2Sb2Te5 films: Effect on “phase-change” stress”, Applied Physics Letters, 90, pp. 141902-1 – 141902-3, April 2007.
  58. [Selected Paper] C. Cabral Jr., K.N. Chen, L. Krusin-Elbaum, and V. Deline, “Irreversible modification of Ge2Sb2Te5 phase change material by nanometers-thin Ti adhesion layers in a device-compatible stack”,  Virtual Journal of Nanoscale Science & Technology, Feb 2007.
  59. C. Cabral Jr., K.N. Chen, L. Krusin-Elbaum, and V. Deline, “Irreversible modification of Ge2Sb2Te5 phase change material by nanometers-thin Ti adhesion layers in a device-compatible stack”, Applied Physics Letters, 90, pp. 051908-1 – 051908-3, 2007.
  60. K. N. Chen, S. M. Chang, L. C. Shen, and R. Reif, “Investigations of Strength of Copper Bonded Wafers with Several Quantitative and Qualitative Tests”, Journal of Electronic Materials, 35(5), pp. 1082-1086, 2006.
  61. K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Bonding Parameters of Blanket Copper Wafer Bonding”, Journal of Electronic Materials, 35(2), pp 230-234, 2006.
  62. [Invited Paper][Review Paper] Kuan-Neng Chen, and R. Reif, “Review Paper: Copper Wafer Bonding: Interface Analysis and Characterization,” Journal of the Chinese Colloid and Interface Society, 28(1), pp. 1-10, 2006.
  63. C. S. Tan, K. N. Chen, A. Fan, and R. Reif, “The effect of forming gas anneal on the oxygen content in bonded copper layer”, Journal of Electronic Materials, 34(12), pp 1598-1602, 2005.
  64. K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Copper Bonded Layers Analysis and Effects of Copper Surface Conditions on Bonding Quality for Three-Dimensional Integration”, Journal of Electronic Materials, 34(12), pp 1464-1467, 2005.
  65. K. N. Chen, S. M. Chang, L. C. Shen, C. S. Tan, A. Fan, and R. Reif, “Processing Development and Bonding Quality Investigations of Silicon Layer Stack Using Copper Wafer Bonding”, Applied Physics Letters, 87(3), pp. 031909-1-031909-3, 2005.
  66. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in 3-D Integration during Current Stressing”, Applied Physics Letters, 86(1), pp. 0011903-1-0011903-3, 2005.
  67. C. S. Tan, K. N. Chen, A. Fan, and R. Reif, “Low temperature direct chemical-vapor-deposition (CVD) oxides to thermal oxide wafer bonding in silicon layer transfer”, Electrochemical and Solid-State Letters, 8(1), pp. G1-G4, 2005.
  68. Kuan-Neng Chen, Mauro J. Kobrinsky, Brandon Barnett and Rafael Reif, “Comparisons of Conventional, 3D, Optical and RF Interconnect for Clock Distribution,” IEEE Trans. on Electron Devices, 51(2), pp 233-239, 2004.
  69. K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration Technology”, IEEE Electron Devices Letters, 25(1), pp 10-12, 2004.
  70. K. N. Chen, C. S. Tan, A. Fan and R. Reif, "Morphology and bond strength of copper wafer bonding", Electrochemical and Solid-State Letters, 7(1), pp G14-G16, 2004.
  71. K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Temperature and Duration Effect on Microstructure Evolution during Copper Wafer Bonding”, Journal of Electronic Materials, 32(12), pp 1371-1374, 2003.
  72. C. S. Tan, A. Fan, K. N. Chen, and R. Reif, “Low temperature thermal oxide to Plasma Enhanced Chemical Vapor Deposition oxide wafer bonding for thin film transfer application,” Applied Physics Letters, 82(16), pp 2649-2651, 2003.
  73. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Microstructure evolution and abnormal grain growth during copper wafer bonding,” Applied Physics Letters, 81(20), pp 3774-3776, 2002.
  74. K. N. Chen, A. Fan, and R. Reif, "Interfacial Morphologies and Possible Mechanisms of Copper Wafer Bonding," Journal of Materials Science, 37(16), pp 3441-3446, 2002.
  75. Kuan-Neng Chen, Andy Fan, and Rafael Reif, "Microstructure Examination of Copper Wafer Bonding," Journal of Electronic Materials, 30, pp 331-335, 2001.
  76. H. H. Lin, K. N. Chen, S. L. Cheng, Y.C. Peng, G.H. Shen, L.J. Chen, and C.R. Chen, “Interfacial Reactions of Metal Thin Films on Ion Implanted Silicon under High Current Density,” J. Korean Phys. Soc. 35, pp S264-266, 1999.
  77. K. N. Chen, H.H. Lin, S.L. Cheng, Y.C. Peng, G.H. Shen, L. J. Chen, C.R. Chen, J.S. Huang, and K.N. Tu, " Silicide Formation in Implanted Channels and Interfacial Reactions of Metal Contacts under High Current Density," Journal of Materials Research. 14, pp 4720-4726, 1999.
  78. Wen-Ku Chang, Shy-Feng Hsieh, Yuan-Haun Lee, Kuan-Neng Chen, Nan-Chung Wu, A. A WANG, "X-ray Diffraction Studies of Phase Transformations Between Tetragonal and Cubic Phases in Ba(Ti,Sn)O3 Systems," Journal of Materials Science, 33(7), pp 1765, 1998.
  79. Po-Fu Yen, Kuan-Neng Chen, and Nan-Chung Wu, “AlN Films Deposited by RF Magnetron Sputtering Techniques,” Proceedings of National Science Council ROC(A) 22, pp. 225-234, 1998.
  80. Kuan-Neng Chen, and Nan-Chung Wu, “The Research and Manufacturing of the Dielectric Materials in (Ba, Ca)(Ti, Sn)O3 System,” Chinese Journal of Materials Science 29, pp. 72-80, 1997.
 Top Conferences(7) 
  1. Yu-Chieh Huang, Yu-Chen Hu, Po-Tsang Huang, Shang-Lin Wu, Yan-Huei You, Jr-Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Ching-Te Chuang, Jin-Chern Chiou, and Kuan-Neng Chen, “Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable µ-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits”, 2016 Symposia on VLSI Technology and Circuits, Honolulu, HI, Jun. 13-17, 2016.
  2. Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Teng-Chieh Huang, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, and Ho-Ming Tong, “2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural Sensing Applications,” 2014 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 9-13, 2014.
  3. Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong, ” Through-Silicon-Via Based Double-Side Integrated Microsystem for Neural Sensing Applications”, 2013 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 13-17, 2013, pp. 102-103.
  4. K. N. Chen, T. M. Shaw, C. Cabral, Jr., and G. Zuo, “Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding”, 2010 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 6-8, 2010.
  5. R. R. Yu, F. Liu, R. J. Polastre, K.-N. Chen, X. H. Liu, L. Shi, E. D. Perfecto, N. R. Klymko, M. S. Chace, T. M. Shaw, D. Dimilia, E. R. Kinser, A. M. Young, S. Purushothaman, S. J. Koester and W. Haensch, “Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding”, 2009 Symposia on VLSI Technology and Circuits, Kyoto, Japan, Jun. 15-18, 2009.
  6. F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K.-N. Chen, X. Li, D. A Dipaola, D. Brown, C. T. Ryan, J. A Hagan, K. Wong, M. Lu, X. Gu, N. Klymko, E. Perfecto, A. G. Merryman, K. Kelly, S. Purushothaman, S. J. Koester, R. Wisneieff, and W. Haensch, “A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding”, 2008 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 15-17, 2008.
  7. Kuan-Neng Chen, Sang Hwui Lee, Paul S. Andry, Cornelia K. Tsang, Anna W. Topol, Yu-Ming Lin, Jian-Qiang Lu, Albert M.Young, Meikei Ieong, and Wilfried Haensch, “Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits”, 2006 International Electron Devices Meeting (IEDM), pp. 367-370, San Francisco CA, Dec. 11-13, 2006.
 Keynote Speech and Tutorial Presentations (1) 
  1. Kuan-Neng Chen, “3D/2.5D Integration: Development of Key Technologies, Current Applications and Trends, and Research Achievements,” 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, Guilin, China, Oct. 28-31, 2014.
 Proceedings and Conference Presentations (142) Invited (37)
  1. Hao-Wen Liang, Ting-Yang Yu, Yao-Jen Chang, and Kuan-Neng Chen, “Asymmetric Low Temperature Bonding Structure Using Ultra-thin Buffer layer Technique for 3D Integration,” 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2016), Singapore, Jul. 18-21, 2016.
  2. Yu-Chen Hu, and Kuan-Neng Chen, “Development and Electrical Performance of Low Temperature Cu-Sn/In Bonding for 3D Flexible Substrate Integration,” IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, Jun. 12-13, 2016.
  3. Yu-Hsiang Huang, Hao-Wen Liang, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, and Kuan-Neng Chen, “Study of a Novel Amorphous Silicon Temporary Bonding and Corresponding Laser Assisted De-bonding Technology,” 2016 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, May 31 – Jun. 3, 2016.
  4. Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Jr-Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou, “An Ultra-High-Density 256-channel/25mm2 Neural Sensing Microsystem using TSV-embedded Neural Probes,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016.
  5. Chuan-An Cheng, Yu-Hsiang Huang, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, and Kuan-Neng Chen, “Wafer-Level MOSFET with Submicron Photolysis Polymer Temporary Bonding Technology Using Ultra-Fast Laser Ablation for 3DIC Application,” 2016 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 25-27, 2016.
  6. Shih-Wei Lee, Shu-Chiao Kuo, and Kuan-Neng Chen, “Electrical Testing Structure for Stacking Error Measurement in 3D Integration,” 2016 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 25-27, 2016.
  7. [Invited] Kuan-Neng Chen, “Development of 3D IC Technologies for Heterogeneous Integration and Neural Sensing Applications,” 2016 International Conference on Electronics Packaging (ICEP) Conference, Sapporo, Japan, Apr. 20-22, 2016.
  8. [Invited] Kuan-Neng Chen, “Research Advances of Low Temperature Bonding Technology in 3D Integration and Heterogeneous Integration,” China Semiconductor Technology International Conference, Shanghai, China, Mar. 13-14, 2016.
  9. [Invited] Chien-Hung Lin, and Kuan-Neng Chen, “Submicron Polymer Temporary Bonding with Ultra-Fast Laser Ablation Application in 3D Semiconductor Package,” China Semiconductor Technology International Conference, Shanghai, China, Mar. 13-14, 2016.
  10. Yu-Hsiang Huang, Yen-Pin Huang, and Kuan-Neng Chen, “Electrical and Stability Investigation of Copper Pillars in 3D LSI Technologies,” International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, Nov 19-20, 2015.
  11. Hsiao-Chun Chang, Cheng-Han Fan, Yi-Chia Chou, and Kuan-Neng Chen, “Study of Self-Assembly Technology for 3D Integration Applications,” IMPACT 2015, Taipei, Taiwan, Oct. 21-23, 2015.
  12. [Invited] Kuan-Neng Chen, “3D IC and Heterogeneous Integration: A Game Changer to Semiconductor, or Not?”, CIE-GNYC 2015 Annual Convention, New York, NY, USA, Oct 17, 2015.
  13. Shu-Lin Lu, Yen-Pin Huang, Yu-Shang Huang, Yi-Hsiu Tseng, Min-Fong Shu, and Kuan-Neng Chen, “Investigation of Low Temperature Cu Pillar Thermosonic Bonding for 3D Integration Applications,” 2015 IEEE International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sep 27-30, 2015.
  14. Cheng-Hsien Lu, Jian-Yu Shih, Yu-Wei Chang, Yi-Tung Kho, and Kuan-Neng Chen, “A Novel Packaging Approach of SAW Devices Using 3D IC Technology,” Symposium on Nano Device Technology, Hsinchu, Taiwan, Sep. 10, 2015.
  15. Chuan-An Cheng, Ryuichi Sugie, Tomoyuki Uchida, Kou-Hua Chen, Chi-Tsung Chiu, and Kuan-Neng Chen, “Electrical Investigation of Cu Pumping in Through-Silicon Vias for BEOL Reliability in 3D Integration,” IEEE 3D System Integration Conference, Sendai, Japan, Aug. 31-Sep 2, 2015.
  16. Tsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, and Kuan-Neng Chen, “An Ultra-Fast Temporary Bonding and Release Process Based on Thin Photolysis Polymer in 3D Integration,” IEEE 3D System Integration Conference, Sendai, Japan, Aug. 31-Sep 2, 2015.
  17. Ting-Yang Yu, Hsin-Cheng Tsai, Shiang-Yu Wang, Chih-Wei Luo, and Kuan-Neng Chen, “High Transmittance Silicon Terahertz Polarizer Using Wafer Bonding Technology,” SPIE Optics + Photonics 2015, San Diego, CA, USA, Aug. 9-13, 2015.
  18. Yu-Wei Chang, and Kuan-Neng Chen, “Fabrication and Reliability Investigation of Copper Pillar and Tapered Through Silicon Via (TSV) for Direct Bonding in 3D Integration,” The 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2015), Hsinchu, Taiwan, Jun. 29 – July 2, 2015.
  19. Tsung-Yen Tsai, Yao-Jen Chang, and Kuan-Neng Chen, “Quality and Reliability Investigation of Ni/Sn Transient Liquid Phase Bonding Technology,” The 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2015), Hsinchu, Taiwan, Jun. 29 – July 2, 2015.
  20. Yu-Sheng Hsieh, Ting-Ting Shen, Yu-San Chien, Yuko Shinozaki, Naohiko Kawasaki, and Kuan-Neng Chen, “Investigation of Low Temperature Cu/In Bonding in 3D Integration,” 2015 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, Jun. 1-4, 2015.
  21. Wen-Wei Shen, Hsiang-Hung Chang, Cheng-Ta Ko, Leon Tsai, Bor Kai Wang, Aric Shorey, Alvin Lee, Jay Su, Baron Chen, Wei-Chung Lo, and Kuan-Neng Chen, “Ultra-thin Glass Wafer Lamination and Laser De-bonding to Enable Glass Interposer Fabrication,” 2015 IEEE Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, May 26 – 29, 2015.
  22. Yu-Chen Hu, Yu-Sheng Hsieh, Anthony J. Gallegos, Wei-Chia Chen and Kuan-Neng Chen, “3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 μm- Technology Nodes,” 2015 IEEE Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, May 26 – 29, 2015.
  23. Y. S. Hsieh, Y. J. Chang, and K. N. Chen, “Development and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D Integration,” 2015 IEEE Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, May 26 –29, 2015.
  24. Yan-Pin Huang, Yu-San Chien, Ruoh-Ning Tzeng, and Kuan-Neng Chen, “Low Temperature Bonding of Cu/Pd-Pd/Cu Interconnects for Three-Dimensional Integration Applications”, 2015 IEEE International Interconnect Technology Conference (IITC), Grenoble, France, May 18 -21, 2015.
  25. [Invited] Kuan-Neng Chen, “Research Achievements and Application Demonstrations of 3D IC and Heterogeneous Integration,” China Semiconductor Technology International Conference, Shanghai, China, Mar 15-16, 2015.
  26. Cheng-Hsien Lu, Yao-Jen Chang, Yu-Sheng Hsieh, Chuan-An Cheng, and Kuan-Neng Chen, “Heterogeneous Integration of Si/GaAs Wafer-Level Polyimide Bonding,” International Electron Devices and Materials Symposium (IEDMS), Hualien, Taiwan, Nov 20-21, 2014.
  27. Jian-Yu Shih, Shih-Wei Lee, Yu-Chen Hu, Yen-Chi Chen, Chih-Hung Chiu, Chi-Chung Chang, and Kuan-Neng Chen, “Advanced Crystal Component Package with Silicon TSV Interposer Using 3D Integration and Novel SU-8 Polymer Sealing Bonding Structure,” IMPACT-EMAP 2014, Taipei, Taiwan, Oct. 22-24, 2014.
  28. [IMPACT-EMAP 2014 Paper Award] Shih-Wei Lee, Jian-Yu Shih, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, and Kuan-Neng Chen, “Polymer TSV Fabrication Scheme with Its Electrical and Reliability Test Vehicle,” IMPACT-EMAP 2014, Taipei, Taiwan, Oct. 22-24, 2014.
  29. [IMPACT-EMAP 2014 Paper Award] Chien-Min Liu, Han-wen Lin, Yi-Sa Huang, Yi-Cheng Chu, Chih Chen, Dian-Rong Lyu, Kuan-Neng Chen, and K. N. Tu, “Low-temperature direct copper-to-copper bonding enabled by creep on highly (111)-oriented Cu surfaces,” IMPACT-EMAP 2014, Taipei, Taiwan, Oct. 22-24, 2014.
  30. Cheng-Han Fan, Yao-Jen Chang, Yi-Chia Chou, and Kuan-Neng Chen, “Interdiffusion of Cu-Sn System with Ni Ultra-thin Buffer Layer and Material Analysis of IMC Growth Mechanism,” IMPACT-EMAP 2014, Taipei, Taiwan, Oct. 22-24, 2014.
  31. Yu-Chen Hu, Yao-Jen Chang, Chun-Shen Wu, Yung Mao Cheng, Wei Jen Chen, and Kuan-Neng Chen, “Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration,” IMPACT-EMAP 2014, Taipei, Taiwan, Oct. 22-24, 2014.
  32. Yao-Jen Chang, and Kuan-Neng Chen, “Development and Material Analyses of Novel Sub-10μm Cu/Sn Wafer Bonding Technology for 3D Integration,” The 40th International Conference on Micro and Nano Engineering (MNE 2014), Lausanne, Switzerland, Sep 22-26, 2014.
  33. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, and Kuan-Neng Chen, “Improvement of Motional Resistance through Concave TSV Design and Modification for Static Capacitance of TSV-Based Resonator,” 2014 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, Sep 8-11, 2014.
  34. Yao-Jen Chang, Yu-Sheng Hsieh, Cheng-Ta Ko, Wei-Chung Lo, Fan-Yi Ouyang, Chun-Shen Wu, Yung Mao Cheng, Wei Jen Chen, and Kuan-Neng Chen, “Joule Heating Induced Bonding Interface Improvement and Ti Breakthrough by Electron Bombardment for 40-μm Pitch of Cu TSV and Cu/Sn μ-Bump Pair”, 2014 International Conference on Solid State Devices and Materials (SSDM 2014), Tsukuba, Japan, Sep 8-11, 2014.
  35. [Invited] Kuan-Neng Chen, “Material Design for Challenging Heterogeneous Applications of 3D IC and Low Temperature Wafer Bonding,” IUMRS-ICEM 2014, Taipei, Taiwan, Jun 10-14, 2014.
  36. [Invited] Chien-Min Liu, Han-Wen Lin, Yi-Sa Huang, Yi-Cheng Chu, Chih Chen, Dian-Rong Lyu, Kuan-Neng Chen, and K. N. Tu, “Low-Temperature and Low-Pressure Direct Copper-to-copper Bonding,” IUMRS-ICEM 2014, Taipei, Taiwan, Jun 10-14, 2014.
  37. Yao-Jen Chang, Cheng-Han Fan, and Kuan-Neng Chen, “Mechanism of Novel Sub-Micron Cu/Sn Bond System with Ultra-Thin Ni Buffer Layer for 3D Integration,” IUMRS-ICEM 2014, Taipei, Taiwan, Jun 10-14, 2014.
  38. J. Y. Shih, W. C. Huang, C. T. Ko, Z. Yang, S. X. Hu, J. P. Leu, K. C. Chou, and K. N. Chen, “Investigations of Interfacial Adhesion between Cu, Al, Co or Ti and Benzocyclobutene (BCB) Polymer Dielectric in 3D Integration,” IUMRS-ICEM 2014, Taipei, Taiwan, Jun 10-14, 2014.
  39. Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, and Wei Hwang, “Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1-5, 2014.
  40. Lei-Chun Chou, Shih-Wei Lee, Po-Tsang Huang, Chih-Wei Chang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, “Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio-Signal Recording Application,” 2014 IEEE Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, May 27 – May 30, 2014.
  41. Shimin Sun, and Kuan-Neng Chen, “A Temporary Bonding/De-Bonding Solution to Realize High Compatibility and Cost Performance in 3D Integration,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE 2014), Taoyuan, Taiwan, May 7-10, 2014.
  42. Tsung-Han Yu, Shih-Wei Lee, and Kuan-Neng Chen, “Development of Adhesive to Oxide Temporary Bonding for 3-D IC Applications,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  43. Wan-Lin Tsai, Kuang-Yu Wang, Yao-Jen Chang, Yun-Shan Chien, Kuan-Neng Chen, Huang-Chung Cheng, “Conductivity enhancement of multiwalled carbon nanotube thin film via thermal compression method,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  44. Chih Chen, Chien-Min Liu, Kuan-Neng Chen, King-Ning Tu, “Low-temperature and low-pressure direct copper-to-copper bonding,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  45. Shu-Chiao Kuo, Shih-Wei Lee, Yao-Jen Chang, Yan-Pin Huang, Ting-Yang Yu, and Kuan-Neng Chen, “Electrical Stacking Error Measurement Structure in Three-Dimensional Integration,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  46. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, Chung-Lun Lo, Chi-Chung Chang, and Kuan-Neng Chen, “Novel Quartz Resonator Device Using TSV, 3D Integration, and Si Hermetic Packaging Technologies,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  47. Chuan-An Cheng, Cheng-Hsien Lu, Dian-Rong Lyu, Yu-Sheng Hsieh, and Kuan-Neng Chen, “Investigation of Low Temperature Polymer Wafer Bonding for Heterogeneous Integration in 3D Application,” IEEE The 3rd International Symposium on Next-Generation Electronics (ISNE), Taoyuan, Taiwan, May 7-10, 2014.
  48. Jian-Yu Shih, Yen-Chi Chen, Chih-Hung Chiu, Chung-Lun Lo, and Kuan-Neng Chen, “A Novel Si-based X’tal Oscillator Device Using 3D Integration Technologies,” 2014 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 28-30, 2014.
  49. Lei-Chun Chou, Shih-Wei Lee, Chuan-An Cheng, Po-Tsang Huang, Chih-Wei Chang, Cheng-Hao Chiang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, “A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array,” 2014 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 28-30, 2014.
  50. Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang and Wei Hwang, “Energy-Efficient Low-Noise 16-Channel Analog Front-End Circuit for Bio-potential Acquisition,” 2014 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 28-30, 2014.
  51. [Invited] Kuan-Neng Chen, “Development of Key Technologies, Schemes, and Applications in 3D/2.5D Integration,” China Semiconductor Technology International Conference, Shanghai, China, Mar 16-17, 2014.
  52. [Invited] Shu-Chiao Kuo, Yao-Jen Chang, Jian-Yu Shih, Cheng-Ta Ko, and Kuan-Neng Chen, “Development and Investigation of 3D Integration Schemes Using TSV, Bonding and Thinning Technologies,” International Electron Devices and Materials Symposium (IEDMS), Nantou, Taiwan, Nov 28-29, 2013.
  53. Ming-Fang Lai, Cheng-Hsien Lu, and Kuan-Neng Chen, “An Overview of ESD Issue with TSV in 3D-IC Fabrication”, 2013 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Nov 4-6, 2013.
  54. Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang and Wei Hwang, “Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications,” 2013 IEEE Biomedical Circuits and Systems Conference (BiOCAS), Rotterdam, the Netherlands,  Oct. 31 – Nov. 2, 2013, pp. 238-241.
  55. Y. P. Huang, Y. S. Chien, R. N. Tzeng, M. S. Shy, T. H. Lin, K. H. Chen, C. T. Chuang, W. Hwang, C. T. Chiu, H. M. Tong, and K. N. Chen, “Low Temperature (<180C) Bonding for 3D Integration ”, IEEE 3D System Integration Conference, San Francisco, CA, USA, Oct. 2-4, 2013.
  56. Yao-Jen Chang, Cheng-Ta Ko, Zhi-Cheng Hsiao, Huan-Chun Fu, Tsung-Han Yu, Wei-Chung Lo, and Kuan-Neng Chen, “Evaluation of Power Dissipation and Delay for New TSV Design Based on Cu/Sn to BCB Hybrid Bonding,” 2013 International Conference on Solid State Devices and Materials (SSDM 2013), Fukuoku, Japan, Sep 24-27, 2013.
  57. Ruoh-Ning Tzeng, Yen-Pin Huang, Yu-San Chien, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, “Low Temperature Bonding of Sn/In-Cu Interconnects for Three-Dimensional Integration Applications,” 2013 IEEE International Interconnect Technology Conference (IITC), Kyoto, Japan, Jun 13-15, 2013.
  58. Jian-Yu Shih, Yen-Chi Chen, Cheng-Hao Chiang, Chih-Hung Chiu, Yu-Chen Hu, Chung-Lun Lo, Chi-Chung Chang, and Kuan-Neng Chen, “TSV-Based Quartz Crystal Resonator Using 3D Integration and Si Packaging Technologies,” 2013 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, May 28 – May 31, 2013.
  59. Y. J. Chang, C. T. Ko, Z. C. Hsiao, J. H. Huang, C. H. Chiang, H. C. Fu, T. H. Yu, F. C. Han, W. C. Lo, K. N. Chen, “Electrical Investigation and Reliability of 3D Integration Platform Using Cu TSVs and μ-bumps with Cu/Sn-BCB Hybrid Bonding,” 2013 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, May 28 – May 31, 2013.
  60. Y. S. Chien, Y. P. Huang, R. N. Tzeng, M. S. Shy, T. H. Lin, K. H. Chen, C. T. Chuang, W. Hwang, C. T. Chiu, H. M. Tong, K. N. Chen, “Low Temperature (<180 C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration,” 2013 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, May 28 – May 31, 2013, pp. 1146-1152.
  61. Ming-Hung Chang, Wei-Chih Hsieh, Pei-Chen Wu, Ching-Te Chuang, Kuan-Neng Chen, Wei Hwang, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong, “Multi-Layer Adaptive Power Management Architecture for TSV 3-D IC Technology,” 2013 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, May 28 – May 31, 2013, pp. 1179-1185.
  62. Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kua-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Wei Hwang, “Near-/Sub-Vth Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection”, 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing China, May 19-23, 2013, pp. 133-136.
  63. Hsiao-Yu Chen, Sheng-Yao Hsu, and Kuan-Neng Chen, “Co-sputtered Cu/Ti Bonded Interconnects for 3D Integration Applications,” The 20th International Symposium on VLSI Technology, Systems and Applications (2013 VLSI-TSA), Hsinchu, Taiwan, Apr 22-24, 2013.
  64. Shih-Wei Lee, Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, "Integration, Electrical Performance and Reliability Investigation of TSV", IMAPS 9th International Conference and Exhibition on Device Packaging, Scottsdale, AZ, USA, Mar 12-14, 2013.
  65. Y. P. Huang, R. N. Tzeng, Y. S. Chien, M. S. Shy, H. S. Chang, T. H. Lin, K. H. Chen, C. T. Chiu, Y. E. Yeh, W. Hwang, C. T. Chuang, J. C. Chiou, H. M. Tong, K. N. Chen, “Low Temperature Cu-Sn and Sn-Sn Bonding Development for 3D Interconnect Applications”, International Electron Devices and Materials Symposium (IEDMS) 2012, Kaohsiung, Taiwan, Nov 29-30, 2012.
  66. Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen,  “Study of TSV Formation with ICP Parameter Control”, Proceedings of the 34th International Symposium on Dry Process, Tokyo, Japan, Nov 15-16, 2012, pp. 127-128.
  67. [Invited] Kuan-Neng Chen, “Fabrication and Evaluation of TSV and Bonded Structures for 3D Integration,” The 7th IMPACT 2012 Conference, Taipei, Taiwan, Oct 24-26, 2012.
  68. Cheng-Hao Chiang, Yu-Chen Hu, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, “Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration”, Proceedings of the 7th IMPACT 2012 Conference, Taipei, Taiwan, Oct 24-26, 2012, pp. 56-59.
  69. Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen,  “Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations”, Proceedings of the 7th IMPACT 2012 Conference, Taipei, Taiwan, Oct 24-26, 2012, pp. 367-369.
  70. Hsing-Han Ho, Cheng-Ta Ko, Yao-Jen Chang, Kuan-Neng Chen, “Investigation of Oxide Bonding from Different Species for 3D Integration and MEMS Applications”, The 7th IMPACT 2012 Conference, Taipei, Taiwan, Oct 24-26, 2012.
  71. [Invited] W. C. Lo, C. Ta Ko, and K. N. Chen, “3D Integration with Wafer-to-Wafer Bonding,” 2012 International Conference on Solid State Devices and Materials (SSDM 2012), Kyoto, Japan, Sep 25-27, 2012.
  72. Chuan-An Cheng, Cheng-Hsien Lu, Chia-Hua Ho, and Kuan-Neng Chen, “Investigation of Electrical Performances for n-MOSFET Devices Integrating with Bonding and Thinning Technologies in 3D Integration,” 2012 International Conference on Solid State Devices and Materials (SSDM 2012), Kyoto, Japan, Sep 25-27, 2012.
  73. [Invited] Kuan-Neng Chen, “Material Analyses and Morphology Investigations of Cu-Based Bonding Technology for 3D Integration,” IUMRS-ICEM 2012, Yokohama, Japan, Sep 23-28, 2012.
  74. Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong and Wei Hwang, “On-Chip Self-Calibrated Process-Temperature Sensor  For TSV 3D Integration”  2012 IEEE International SoC Conference (SOCC), Niagara Falls, NY, USA, Sept. 12 -14, 2012, pp. 370-375.
  75. Po-Tsang Huang, Tzu-Ting Chiang, Herming Chiueh, Ching-Te Chuang, Jin-Chern Chiou, Kuan-Neng Chen, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Wei Hwang, “Thermal Management with In-Situ Process-Temperature Sensor for TSV 3D-ICs”, The 23rd VLSI Design/CAD Symposium, Kenting, Taiwan, Aug 7-10, 2012.
  76. [Invited] Kuan-Neng Chen, “Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects,” 2012 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, Jun 03-06, 2012.
  77. C. T. Ko, Z. C. Hsiao, Y. J. Chang, P. S. Chen, J. H. Huang, H. C. Fu, Y. J. Huang, C. W. Chiang, C. K. Lee, H. H. Chang, W. L. Tsai, S. H. Wu, S. S. Sheu, Y. H. Chen, W. C. Lo, and K. N. Chen, “Structural Design, Process, and Reliability of a Wafer-Level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Wafer Bonding,” Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, May 29 - Jun 1, 2012.
  78. Y. J. Chang, C. T. Ko, Z. C. Hsiao, T. H. Yu, Y. H. Chen, W. C. Lo, and K. N. Chen, “Electrical Characterization and Reliability Investigations of Cu TSVs with Wafer-Level Cu/Sn-BCB Hybrid Bonding,” The 19th International Symposium on VLSI Technology, Systems and Applications (2012 VLSI-TSA), Hsinchu, Taiwan, Apr. 23-25, 2012.
  79. [Invited] Kuan-Neng Chen, “Key Technologies of 3D Integration: Schemes, Achievements, and Outlook”, China Semiconductor Technology International Conference 2012, Shanghai, China, Mar 18-19, 2012.
  80. K. N. Chen, Z. Xu, F. Liu, C. T. Ko, C. A. Cheng, W. C. Huang, H. L. Lin, C. Cabral, Z. C. Hsiao, N. Klymko, H. C. Fu, Y. H. Chen, J. Q. Lu, and W. C. Lo “Cu-Based Bonding Technology for 3D Integration Applications”, IEEE 3D System Integration Conference, Osaka, Japan, Jan 31 – Feb 2, 2012.
  81. C. T. Ko, Z. C. Hsiao, Y. J. Chang, P. S. Chen, J. H. Huang, H. C. Fu, Y. J. Huang, C. W. Chiang, W. L. Tsai, Y. H. Chen, W. C. Lo, and K. N. Chen, “Wafer-Level 3D Integration with Cu TSV and Micro-bump/Adhesive Hybrid Bonding Technologies”, IEEE 3D System Integration Conference, Osaka, Japan, Jan 31 – Feb 2, 2012.
  82. [Invited] Kuan-Neng Chen, “Three-Dimensional Integrated Circuits (3D IC): Schemes, Technologies, and Recent Research Achievements”, International Electron Devices and Materials Symposium (IEDMS) 2011, Taipei, Taiwan, Nov 17-18, 2011.
  83. Yen-Pin Huang, Chuan-An Cheng, Cho-Lun Hsu, Chia-Hua Ho, and Kuan-Neng Chen, “Achievement of Dense Through Silicon Via (TSV) for 3D Integration by Micro-Masking Free Process”, International Electron Devices and Materials Symposium (IEDMS) 2011, Taipei, Taiwan, Nov 17-18, 2011.
  84. [Invited] Kuan-Neng Chen, “Schemes, Achievements, and Challenges of Key Technologies in Three-Dimensional Integrated Circuits (3D IC)”, The 13th Photonics and Semiconductor Device Reliability Workshop, Hsinchu, Taiwan, Nov 4, 2011.
  85. W. C. Huang, C. T. Ko, S. H. Hu, J. P. Leu, and K. N. Chen, “Investigations of Adhesion between Cu and Benzocyclobutene (BCB) Polymer Dielectric for 3D Integration Applications”, International Microsystems, Packaging, Assembly, and Circuit Technology Conference (IMPACT 2011), Taipei, Taiwan, Oct. 18-21, 2011.
  86. [Invited] Kuan-Neng Chen, “Wafer-Level Hybrid Bonding for 3D Integration”, IUMRS-ICA 2011, Taipei, Taiwan, Sep 19-22, 2011.
  87. [Invited] Kuan-Neng Chen and Chuan Seng Tan, “3-D Integration: Materials, Technologies, Schemes, and Applications”, 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sep 18-21, 2011.
  88. S. Y. Hsu, J. Y. Shih, and K. N. Chen, “Diffusion Behavior and Mechanism of Co-Sputtering Metals as Bonding Materials for 3D IC Interconnects during Annealing Treatment”, 2011 IEEE International Nano Electronic Conference (INEC), Tao-Yuan, Taiwan, Jun 21-24, 2011.
  89. S. L. Lin, W. C. Huang, and K. N. Chen, “Studies of Oxide to Polymer Bonding for 3D IC”, 2011 IEEE International Nano Electronic Conference (INEC), Tao-Yuan, Taiwan, Jun 21-24, 2011.
  90. C. A. Cheng, C. T. Ko, and K. N. Chen, “Investigation of bonding temperature for SU-8 materials in wafer-level hybrid bonding technology for 3D IC”, 2011 IEEE International Nano Electronic Conference (INEC), Tao-Yuan, Taiwan, Jun 21-24, 2011.
  91. [Invited] Kuan-Neng Chen, “Three-Dimensional Integrated Circuits (3D IC): Concept, Technology, and Outlook”, 18TH Symposium on Nano Device Technology (SNDT), Hsinchu, Taiwan, Apr. 21-22, 2011.
  92. K. N. Chen, C. A. Cheng, W. C. Huang, and C. T. Ko, “Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration”, 2011 TMS Meeting, San Diego, CA, Feb 27-Mar. 3, 2011.
  93. [Invited] Kuan-Neng Chen, “Taiwan Research and Development Activities for 3D Integrated Circuits”, 2010 International Conference of 3-D Architectures for Semiconductor Integration and Packaging, San Francisco CA, Dec. 8-10, 2010.
  94. Cheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo, Chuan-An Cheng, Wen-Chun Huang, Zhi-Cheng Hsiao, Huan-Chun Fu, and Yu-Hua Chen, “Wafer-Level 3D Integration Using Hybrid Bonding”, IEEE 3D IC International Conference, Munich, Germany, Nov. 16-18, 2010.
  95. Zheng Xu, Adam Beece, Dingyou Zhang, Qianwen Chen, Kuan-neng Chen, Kenneth Rose, and Jian-Qiang Lu, “Crosstalk Evaluation, Suppression and Modeling in 3D Through-Strata-Via (TSV) Network”, IEEE 3D IC International Conference, Munich, Germany, Nov. 16-18, 2010.
  96. Ming-Fang Lai, Shu-Chuan Chen, Yen-Hsien Chen, Yu-Ti Su, Che-Hung Chen, Po-An Chen, Hung-Ming Chen and Kuan-Neng Chen, “Area Efficient I/O Circuit in High Pin Count IC”, 2010 Taiwan ESD and Reliability Conference, Hsinchu, Taiwan, Oct. 25-27, 2010.
  97. Cheng-Ta Ko, Zhi-Cheng Hsiao, Huan-Chun Fu, Kuan-Neng Chen, Wei-Chung Lo, and Yu-Hua Chen, “Wafer-to-Wafer Hybrid Bonding Technology for 3D IC”, Electronics System Integration Technology Conferences (ESTC 2010), Berlin, Germany, Sep. 13-16, 2010.
  98. Kuan-Neng Chen, Ming-Fang Lai, and Hung-Ming Chen, “Wafer-Level Three-Dimensional Integrated Circuits (3D IC): Schemes and Key Technologies”, IUMRS-ICEM, Seoul, Korea, Aug. 22-27, 2010.
  99. K. N. Chen, C. Cabral, Jr., S. H. Lee, P. S. Andry, and J. Q. Lu, “Investigations of Cu Bond Structures and Demonstration of a Wafer-Level 3D Integration Scheme with W TSVs”, The 17th International Symposium on VLSI Technology, Systems and Applications (2010 VLSI-TSA), Hsinchu, Taiwan, Apr. 26-28, 2010.
  100. K. N. Chen, Y. Zhu, W.W. Wu, and R. Reif, “Investigation and Effects of Wafer Bow in Different 3D Stacking Schemes”, 2010 TMS, Seattle, WA, Feb 14-18, 2010.
  101. Cheng-Ta Ko, Wei-Chung Lo, Kuan-Neng Chen, Huan-Chun Fu, Zhi-Cheng, Hsiao, and Yu-Hua Chen “Polymers Investigation for 3D IC Stacking Technology”, 2010 TMS Meeting, Seattle, WA, Feb 14-18, 2010.
  102. K. N. Chen, Y. Zhu, W. W. Wu, C. K. Tsang, S. H. Lee, and J. Q. Lu, “Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration Applications”, IEEE International NanoElectronics Conference (INEC) 2010, Hong Kong, Jan 3-8, 2010.
  103. W. W. Wu, K. C. Lu, K. N. Chen, and C. W. Wang, “Controlled large strain of Si in the NiSi/Si/NiSi nanowire heterostructure”, IEEE International NanoElectronics Conference (INEC) 2010, Hong Kong, Jan 3-8, 2010.
  104. K.N. Chen, Y. Zhu, W.W. Wu, and R. Reif, “Copper Thin Film Research and Development for Wafer Bonding”, TACT 2009 International Thin Films Conference, Taipei, Taiwan, Dec 14-16, 2009.
  105. W.W. Wu, K.N. Chen, and C. W. Wang, “Enhanced growth of low-resistivity titanium silicides on epitaxial Si0.7Ge0.3 on (001)Si with a sacrificial amorphous Si interlayer”, TACT 2009 International Thin Films Conference, Taipei, Taiwan, Dec 14-16, 2009.
  106. [Invited] Kuan-Neng Chen, “Wafer-Level Alignment Technology for 3D Integration”, The 4th IMPACT 2009 Conference and International 3D IC Conference, Taipei, Taiwan, Oct. 21-23, 2009.
  107. [Invited] Chuan Seng Tan and Kuan-Neng Chen, “Low Temperature Cu-Cu Bonding and Hybrid Cu/Dielectric Bonding: An Enabling Technology for 3-D ICs Application”, The 4th IMPACT 2009 Conference and International 3D IC Conference, Taipei, Taiwan, Oct. 21-23, 2009.
  108. [Invited] Kuan-Neng Chen, “Wafer-Level Copper Bonding Technology in 3D ICs”, 216th ECS Meeting, Vienna, Austria, Oct. 4-9, 2009.
  109. K.N. Chen and L. Krusin-Elbaum, “CMOS-Technology Compatible Programmable Via using Phase-Change Materials”, 2009 Nano and Giga Challenges in Electronics, Photonics and Renewable Energy, Hamilton, Ontario, Canada, Aug 10-14, 2009.
  110. K.N. Chen, E.A. Joseph, J.C. Arnold, and N. Ruiz, “Fabrication of robust self-aligned nano-scale tubular structures and templates for device applications”, 2009 Nano and Giga Challenges in Electronics, Photonics and Renewable Energy, Hamilton, Ontario, Canada, Aug 10-14, 2009.
  111. K.N. Chen, C. Cabral Jr., L. Krusin-Elbaum, “Segregation of Te and Irreversible Modification in Ge2Sb2Te5 Phase Change Material”, E-MRS 2008 Spring Meeting, Strasburg, France, May 26-30, 2008.
  112. Sang Hwui Lee, Kuan-Neng Chen, Douglas C. La Tulipe, Albert M. Young, and Jian-Qiang Lu, “Thermal Process Induced Wafer-to-Wafer Misalignment for 3D Interconnects”, 2008 International Conference and Exhibition on Device Packaging, Scottsdale AZ, March 17-20, 2008.
  113. Albert M. Young, Douglas C. La Tulipe, Leathen Shi, Kuan-Neng Chen, Roy R. Yu, and Steven J. Koester, “Critical process technologies in 3D integration”, Government Microcircuit Applications & Critical Technology Conference, Las Vegas NV, March 17-20, 2008.
  114. [Invited] Kuan-Neng Chen, “Science, Materials, and Process Technology of Cu Bonding for 3D Integration”, 2007 International Conference and Exhibition on Device Packaging, Scottsdale AZ, March 19-22, 2007.
  115. C. Cabral Jr., L. Krusin-Elbaum, K.N. Chen, M. Copel, J. Bruley, V.R. Deline, “Evidence for segregation of Te in “phase-change” thin chalcogenide Ge-Sb-Te films”, APS March Meeting 2007, Denver CO, March 5-9, 2007.
  116. [Invited] C. S. Tan, K. N. Chen, A. Fan, A. Chandrakasan, and R. Reif, “Silicon Layer Stacking Enabled by Wafer Bonding,” Materials Research Society Symposium Proceedings 970, pp. 193-204, Boston, MA, Nov 27 – Dec 1, 2006
  117. [Invited] K.N. Chen, C.K. Tsang, A.W. Topol, S.H. Lee, B.K. Furman, D.L. Rath, J.-Q. Lu, A.M. Young, S. Purushothaman, and W. Haensch, “Improved Manufacturability of Cu Bond Pads and Implementation of Seal Design in 3D Integrated Circuits and Packages”, 23rd International VLSI Multilevel Interconnection (VMIC) Conference, Fremont CA, Sep.25-28, 2006.
  118. Kuan-Neng Chen, Muhannad Bakir, James Meindl, and Rafael Reif, “Copper Interconnect Bonding for Polymer Pillar I/O Interconnects and Three-Dimensional (3D) Integration Application”, 2006 Electronic Materials Conference, University PA, June 28-30, 2006.
  119. K. N. Chen, and R. Reif, “Wafer Bow and Copper Wafer Bonding”, APS March Meeting 2006, Baltimore MD, March 13-17, 2006.
  120. [Invited] Kuan-Neng Chen, “Copper Wafer Bonding for 3D Integration,” IBM 3D Silicon Workshop on Silicon, Through Vias, Packaging and Module Assemblies, Yorktown Heights NY, March 7, 2006.
  121. K. N. Chen, L Krusin-Elbaum, C. Cabral, C. Lavoie, J. Sun, S. Rossnagel, “Thermal stress evaluation of a PCRAM material Ge2Sb2Te5”, 21st IEEE NVSMW (Non-Volatile Semiconductor Memory Workshop), pp. 97-98, Monterey CA, February 12-16, 2006.
  122. C. S. Tan, K. N. Chen, A. Fan, and R. Reif, “A Back-to-Face Silicon Layer Stacking for Three-Dimensional Integration”, Proceedings of  2005 IEEE International SOI Conference, pp. 87-89, Honolulu Hi, October 3-6, 2005.
  123. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Copper Wafer Bonding: Interface Analysis and Characterization”, Microscopy and Microanalysis 2005, Honolulu Hi, July 31 –Aug. 4, 2005.
  124. [Invited] R. Gutmann, J. Lu, J. Yu, K. -N. Chen, and R. Reif, "Copper Metallization Needs for Wafer-Level, Three-Dimensional Integration", 207th ECS meeting, Quebec City, Canada, May 15-20, 2005.
  125. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Effects of surface roughness and oxide formation of Cu film on the quality of Cu wafer bonding”, 2005 TMS meeting, San Francisco CA, February 13-17, 2005.
  126. [Invited] K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Bonding parameters of Cu wafer bonding for 3D Integration”, 2005 TMS meeting, San Francisco CA, February 13-17, 2005.
  127. K. N. Chen, S. M. Chang, L. C. Shen and R. Reif, “Using different test techniques to investigate the bond strength of Cu wafer bonding”, 2005 TMS meeting, San Francisco CA, February 13-17, 2005.
  128. C. S. Tan, A. Fan, K. N. Chen, and R. Reif, “Multilayered Three-Dimensional Integration Enabled by Wafer Bonding,” SRC/ISMT 7th Annual Topical Research Conference on Reliability, University of Texas, Austin, TX, October 25-27, pp. 27, 2004.
  129. [Invited] R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "Technology and Applications of Three-Dimensional Integration,” 206th Electrochemical Society Fall Meeting, Honolulu, Hawaii, October 3-8, 2004. In Dielectrics for Nanosystems: Materials, Science, Processing, Reliability, and Manufacturing, R. Singh, H. Iwai, R. R. Tummala, and S. C. Sun, Editors, PV 2004-04, The Electrochemical Society Proceedings Series, Pennington, NJ, 2004.
  130. [Invited] R. Reif, S. Das, A. Fan, K.-N. Chen, C. S. Tan, and N. Checka, “Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits,” International Symposium on Physical Design (ISPD 2004), Phoenix, Arizona, April 18-21, 2004.
  131. [Invited] R. Reif, C.S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "Technology and Applications of Three-Dimensional Integration,” Pre-conference Symposium, RTI/ISMT 3D Architectures for Semiconductor Integration and Packaging Conference, April 13-15, 2004, Burlingame, CA.
  132. [Invited] R. Reif, C. S. Tan, A. Fan, and K. N. Chen, “Three-dimensional Integration Enabled by Wafer Bonding and Layer Transfer,” Applied Materials Inc Workshop, Santa Clara, CA, January 16, 2004.
  133. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Abnormal Contact Resistance Reduction in Bonded Cu Interconnects Using Pre-Bonding HCl Cleaning", MRS Fall Meeting, Boston MA, December 2003.
  134. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Relation of Contact Resistance Reduction and Process Parameters of Bonded Copper Interconnects in Three-Dimensional Integration Technology”, Proceedings of 2003 ECS meeting, Orlando FL, October 2003.
  135. K. N. Chen, Andy Fan, Chuan Seng Tan, and Rafael Reif, “Evolution of Microstructure During Copper Wafer Bonding”, 2003 TMS meeting, San Diego CA, March 2003.
  136. [Invited] R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, “3-D Interconnects Using Cu Wafer Bonding : Technology and Applications,” Adcanced Metallization Conference (AMC), October 1-3, 2002, San Diego, CA. In Melnick et al, Advanced Metallization Conference 2002, Materials Research Society, pp 37-45, Spring 2003.
  137. [Invited] R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "3-D Integration using Cu-Cu Wafer Bonding," DARPA 3-D Microelectronics Integration Workshop, San Diego, CA, July 10, 2002.
  138. A. Fan, S. Das, K. N. Chen, and R. Reif, “Fabrication Technologies for Three-Dimensional Integrated Circuits,” IEEE International Symposium on Quality Electronic Design, pp. 33-37, 2002.
  139. [Invited] A. Fan, K. N. Chen, and R. Reif, “Three-Dimensional Integration with Copper Wafer Bonding”, Electrochemical Society Spring Meeting, ULSI Process Integration Symposium, pp. 124-132, Proceedings Volume 2001-2, Washington D.C., March 25-29, 2001.
  140. Woei Wu Pai, Y. H. Peng, W. F. Chung, S. Y. Wang, K. N. Chen, and H. H. Cheng, "Unusual Surface Undulations Observed in Low Temperature Ge/Si(100) Epitaxy", MRS fall meeting proceedings, Session P10.7, Boston MA, December 2000.
  141. H. H. Lin, K. N. Chen, S. L. Cheng, Y.C. Peng, G.H. Shen, L.J. Chen, and C.R. Chen, "Interfacial Reaction of Metal Thin Films on Ion Implanted Silicon Under High Current Density", IUMRS-ICEM-98, Korea.
  142. [Invited] L. J. Chen, K. N. Chen, H. H. Lin; S. L. Cheng, Y. C. Peng, G. H. Shen, C.R. Chen, "Silicide Formation in Implanted Channels and Polarity Effects of Ni and Co Contacts Under High Current Density", IEEE International Conference on Ion Implantation Technology, Kyoto, Japan, pp. 837-840, June 1998.
Patent  
Issued Patent (76)
  1. Wen-Wei Shen, Kuan-Neng Chen, and Cheng-Ta Ko, “Semiconductor Device, Manufacturing Method and Stacking Structure Thereof,” U.S. Patent 9,373,564, filed on Mar. 6, 2015, Issue Date: Jun. 21, 2016.
  2. Kuo-Hua Chen, Tzu-Hua Lin, Kuan-Neng Chen, and Yan-Pin Huang, “Semiconductor Bonding Structure,” U.S. Patent 9,196,595, filed on Feb. 27, 2014, Issue Date: Nov. 24, 2015.
  3. Kuan-Neng Chen, Yao-Jen Chang, “Submicron Connection Layer and Method for Using The Same to Connect Wafers”, U.S. Patent 8,951,837, filed on Sep. 6, 2012, Issue Date: Feb. 10, 2015.
  4. Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric,” U.S. Patent 8,927,087, filed on Sep. 17, 2013, Issue Date: Jan. 6, 2015.
  5. Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,900,918, filed on May 2, 2013, Issue Date: Dec. 2, 2014.
  6. Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof,” U.S. Patent 8,878,193, filed on May 2, 2013, Issue Date: Nov. 4, 2014.
  7. Chi-Chung Chang, Chih-Hung Chiu, Yen-Chi Chen, Kuan-Neng Chen, Jian-Yu Shih, “Through Silicon Via-Based Oscillator Wafer-level-package Structure and Method for Fabricating the Same,” U.S. Patent 8,766,734, filed on Jun. 22, 2012, Issue Date: Jul. 1, 2014.
  8. Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,698,165, filed on May 2, 2013, Issued Date: Apr. 15, 2014.
  9. Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method for Fabricating the Same,” U.S. Patent 8,679,891, filed on Jan 2, 2014, Issue Date: Mar. 25, 2014.
  10. Kuan-Neng Chen, Ming-Fang Lai, and Hung-Ming Chen, “Integrated Circuit Device”, U.S. Patent 8,653,641, filed on Sep. 13, 2012, Issue Date: Feb. 18, 2014.
  11. Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric and Structures So Formed,” U.S. Patent 8,617,689, filed on Apr. 10, 2012, Issue Date: Dec. 31, 2013.
  12. Kuan-Neng Chen, and Fei Liu, “Precise-aligned lock-and-key bonding structures”, U.S. Patent 8,603,862, filed on May 14, 2010, Issue Date: Dec. 10, 2013.
  13. Kuan-Neng Chen, Shih-Wei Li, “Stacking Error Measurement with Electrical Test Structure Applying 3D-ICs Bonding Technology”, U.S. Patent 8,546,952, filed on Nov. 11, 2011, Issue Date: Oct. 1, 2013.
  14. Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method For Fabricating the Same,“ U.S. Patent 8,536,613, filed on Sep 2, 2011, Issue Date: Sep. 17, 2013.
  15. Kuan-Neng Chen, and Sampath Purushothaman, “Programmable via devices”, U.S. Patent 8,525,144, filed on Jul. 29, 2009, Issue Date: Sep. 3, 2013.
  16. Kuan-Neng Chen, Sheng-Yao Hsu, “Bonding Method for Three-Dimensional Integrated Circuit and Three-Dimensional Integrated Circuit Thereof”, U.S. Patent 8,508,041, filed on Dec. 14, 2011, Issued Date: Aug. 13, 2013.
  17. Phaedon Avouris, Kuan-Neng Chen, and Yu-Ming Lin, “Method to fabricate high performance carbon nanotube transistor integrated circuits by 3D integration technology”, U.S. Patent 8,455,297, filed on July 7, 2010, Issued Date: Jun. 4, 2013.
  18. Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,445,320, filed on May 20, 2010, Issued Date: May 21, 2013.
  19. Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Three-dimensional integrated circuits and techniques for fabrication thereof”, U.S. Patent 8,426,921, filed on Feb 1, 2011, Issued Date: Apr. 23, 2013.
  20. Bruce G. Elmegreen, Lia Krusin-Elbaum, Glenn J. Martna, Xiao Hu Liu, Dennis M. Newns, and Kuan-Neng Chen, “Coupling piezoelectric material generated stresses to devices formed in integrated circuits”, U.S. Patent 8,405,279, filed on Jun. 26, 2012, Issued Date: Mar. 26, 2013.
  21. Kuan-Neng Chen, and Sampath Purushothaman, “Programmable via devices”, U.S. Patent 8,389,967, filed on Oct. 18, 2007, Issued Date: Mar. 5, 2013.
  22. Bruce G. Elmegreen, Lia Krusin-Elbaum, Glenn J. Martna, Xiao Hu Liu, Dennis M. Newns, and Kuan-Neng Chen, “Coupling piezoelectric material generated stresses to devices formed in integrated circuits”, U.S. Patent 8,247,947, filed on Dec. 7, 2009, Issued Date: Aug. 21, 2012.
  23. Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices in back of line level”, U.S. Patent 8,243,507, filed on May 13, 2011, Issue Date: Aug. 21, 2012.
  24. Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric,” U.S. Patent 8,241,995, filed on Sep. 18, 2006, Issue Date: Aug. 14, 2012.
  25. Kuan-Neng Chen, John Arnold and Niranja Ruiz, “Methods of forming tubular objects”, U.S. Patent 8,168,542, filed on Jan 3, 2008, Issue Date: May 1, 2012.
  26. Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Techniques for three-dimensional circuit integration”, U.S. Patent 8,129,811, filed on Apr 16, 2011, Issue Date: Dec 13, 2011.
  27. Kuan-Neng Chen, and Fei Liu, “Scalable transfer-join bonding lock-and-key structures”, U.S. Patent 8,076,177, filed on May 14, 2010, Issue Date: Dec 13, 2011.
  28. Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 8,053,752, filed on Jan. 8 2011, Issue Date: Nov 8, 2011.
  29. Kuan-Neng Chen, John Arnold, and Niranjana Ruiz, “Methods of forming features in integrated circuits”, U.S. Patent 8,012,811, Filing Date: Jan 3, 2008, Issue Date: Sep 6, 2011.
  30. Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,982,203, Filing Date: Feb 1, 2010, Issue Date: Jul 19, 2011.
  31. Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices with air gap isolation”, U.S. Patent 7,977,203, Filing Date: Aug 20, 2009, Issue Date: Jul 12, 2011.
  32. Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices in back of line level”, U.S. Patent 7,969,770, Filing Date: Aug. 3, 2007, Issue Date: Jun. 28, 2011.
  33. Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Techniques for three-dimensional circuit integration”, U.S. Patent 7,955,887, Filing Date: Jun. 3, 2008, Issue Date: Jun. 7, 2011.
  34. Matthew J. Breitwisch and Kuan-Neng Chen, “Wafer bonded access device for multi-layer phase change memory using lock-and-key alignment”, U.S. Patent 7,927,911, Filing Date: Aug. 28, 2009, Issue Date: Apr. 19, 2011.
  35. Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Three-dimensional integrated circuits and techniques for fabrication thereof”, U.S. Patent 7,897,428,  Filing Date: Jun 3, 2008, Issue Date: Mar 1, 2011.
  36. Kuan-Neng Chen, Lia Krusin-Elbaum, Chung H. Lam, and Albert M. Young, “Programmable Via Structure and Method of Fabricating Same”, U.S. Patent 7,888,164, Filing Date: Aug 8, 2009, Issue Date: Feb 15, 2011.
  37. Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 7,880,157, Filing Date: Aug 19, 2009, Issue Date:  Feb 1, 2011.
  38. Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,811,933, Filing Date: Feb 1, 2010, Issue Date:  Oct 12, 2010.
  39. Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, and Albert M. Young, “Hermetic Seal and Reliable Bonding Structures for 3D Applications”, U.S. Patent 7,786,596, Filing Date: Feb 27, 2008, Issue Date: Aug 31, 2010.
  40. Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 7,772,582, Filing Date: July 11, 2007, Issue Date: Aug 10, 2010.
  41. Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,687,309, Filing Date: Jun 28, 2007, Issue Date: Mar 30, 2010.
  42. Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, and Albert M. Young, “Hermetic Seal and Reliable Bonding Structures for 3D Applications”, U.S. Patent 7,683,478, Filing Date: Feb 6, 2008, Issue Date: Mar 23, 2010.
  43. Kuan-Neng Chen, Dennis Newns, Sampath Purushothaman, and Lia Krusn-Elbaum, “Programmable via devices with air gap isolation”, U.S. Patent 7,659,534, Filing Date: Aug 3, 2007, Issue Date: Feb 9, 2010.
  44. Kuan-Neng Chen, Lia Krusin-Elbaum, Chung H. Lam, and Albert M. Young, “Programmable Via Structure and Method of Fabricating Same”, U.S. Patent 7,652,278, Filing Date: Dec 19, 2006, Issue Date: Jan 26, 2010.
  45. Kuang-Neng Chen, Bruce G. Elmegreen, Doek-Kee Kim, Chandrasekharan Kothandaraman, Lia Krusin-Elbaum, Chung H. Lam, Dennis Newns, Byeongju Park, and Sampath Purushothaman, “Programmable fuse/non-volatile memory structures in BEOL regions using externally heated phase change material”, U.S. Patent 7,633,079 , Filing Date: Sep. 6, 2007, Issue Date: Dec. 15, 2009.
  46. Kuan-Neng Chen, and Chung H. Lam, “Switch array of circuit and system using programmable via structures with phase change materials”, U.S. Patent 7,608,851, Filing Date: May 8, 2007, Issue Date: Oct 27, 2009.
  47. Kuan-Neng Chen, and Chung H. Lam, “Four-terminal programmable via-containing structure and method of fabricating same”, U.S. Patent 7,579,616, Filing Date: Apr 10, 2007, Issue Date: Aug 25, 2009.
  48. Rafael Reif, Kuan-Neng Chen, Chuan Seng Tan, and Andy Fan, “Method of Forming a Multi-Layer Semiconductor Structure Incorporating a Processing Handle Member,” U.S. Patent 7,307,003, Filing Date: Dec 30, 2003, Issue Date: Dec 11, 2007.  
  49. 陳冠能, 李世偉, “三次元集積回路”, Japan Patent No. 5624081, filed on May 22, 2012, Issue Date: Oct 3, 2014.  
  50. 陳冠能, 徐聖堯, “三維積體電路之接合方法及其三維積體電路”, Korea Patent No. 10-1384131, filed on Feb. 3, 2012, Issue Date: Apr. 4, 2014.
  51. 陳冠能, 李世偉, “Stacking Error Measurement with Electrical Test Structure Applying 3D-ICs Bonding Technology”, Korea Patent Application No. 10-1373267, filed on Nov. 10, 2011, Issue Date: Mar. 5, 2014.
  52. Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method For Fabricating the Same,“ Korean Patent 10-1259308, filed on Aug 31, 2011, Issue Date: Apr. 23, 2013.
  53. Kuan-Neng Chen, Ming-Fang Lai, and Hung-Ming Chen, “ESD Protection Structure for 3D IC”, Korea Patent 10-1227872, filed on Apr. 20, 2011, Issued Date: Jan. 24, 2013.  
  54. 陳冠能, 張耀仁“半導體元件之內連接結構”, 中華民國發明專利 I509758, filed on Jul. 30, 2013, Issued Date: Dec. 1, 2015.
  55. 譚盎南, 陳宏明, 陳冠能,“三維積體電路”, 中華民國發明專利 I509758, filed on Dec. 26, 2012, Issued Date: Nov. 21, 2015.
  56. 張祺鐘, 邱智宏, 陳彥崎, 陳冠能, 施建宇,“貫孔式振子裝置晶圓級封裝結構及其製造方法”, 中華民國發明專利 I498951, filed on Apr. 27, 2012, Issued Date: Sep. 1, 2015.
  57. 阿弗瑞斯　飛登 Phaedon Avouris, 陳冠能 Kuan-Neng Chen, 法墨　戴蒙 Damon Farmer, 林佑明 Yu-Ming Lin, “以石墨烯為基底的元件及其製造方法Graphene Channel-Based Devices and Methods for Fabrication Thereof”, 中華民國發明專利 I497644, filed on May 20, 2011, Issued Date: Aug. 21, 2015.
  58. 陳冠能, 張耀仁,“晶圓次微米接合方法及其接合層,” 中華民國發明專利 I476839, filed on Jul. 6, 2012, Issued Date: Mar. 11, 2015.
  59. 陳冠能, 賴明芳, 陳宏明,“立體積體電路裝置”, 中華民國發明專利 I467736, filed on Jan. 4, 2012, Issued Date: Jan. 1, 2015.
  60. 陳冠能, 李世偉, “三維積體電路”, 中華民國發明專利 I443803, filed on Sep. 9, 2011, Issued Date: Jul. 1, 2014.
  61. 陳冠能, 柯正達, 駱韋仲, “具有積體電路與發光二極體之異質整合結構及其製作方法”, 中華民國發明專利 I434405, filed on Jun. 7, 2011, Issued Date: Apr. 11, 2014.
  62. 陳冠能, 徐聖堯, “三維積體電路之接合方法及其三維積體電路”, 中華民國發明專利 I433268, filed on Sep. 16, 2011, Issued Date: Apr. 1, 2014.
  63. 陳冠能,羅中倫,藍文安,陽明益,“強化氣密性之振子裝置晶圓級封裝結構”,中華民國發明專利 I422080, filed on Aug. 20, 2010, Issued Date: Jan. 1, 2014.
  64. 陳冠能,賴明芳,陳宏明,“三維積體電路的靜電防護結構”, 中華民國發明專利 I416706, filed on Dec. 20, 2010, Issued Date: Nov. 21, 2013.
  65. 陳冠能,羅中倫,藍文安,陽明益,“改良式振子晶圓級封裝結構”, 中華民國發明專利 I412167, filed on Aug. 20, 2010, Issued Date: Oct. 11, 2013.
  66. 陳冠能,羅中倫,藍文安,陽明益,“貫孔式振子裝置晶圓級封裝結構之製造方法”, 中華民國發明專利 I396311, filed on Aug. 20, 2010, Issued Date: May 11, 2013.
  67. 張祺鐘, 邱智宏, 陳彥崎, 陳冠能, 施建宇,“具有凹槽之振子單元封裝結構”, 中華民國新型專利 M438707, filed on May 1, 2012, Issued Date: Oct. 1, 2012.
  68. 張祺鐘, 邱智宏, 陳彥崎, 陳冠能, 施建宇, “貫孔式振子裝置晶圓級封裝結構”, 中華民國新型專利 M437527, filed on May 1, 2012, Issued Date: Sep. 11, 2012.  
  69. 刘小虎, D. 纽恩斯, L. 克鲁辛-伊-鲍姆, G. J. 马丁纳, B. G. 埃尔姆格林, 陈冠能,“耦合结构及其形成方法”, SIPO Patent CN 102640314 B, filed on Dec. 3, 2010, Issued Date: May 7, 2014.
  70. 林慈桦, 陈国华, 陈冠能,“封装载体结构”, SIPO Patent CN 102623429, filed on Apr. 11, 2012, Issued Date: Aug. 1, 2012.
  71. 陈冠能, 柯正达, 骆韦仲,“具有集成电路与发光二极管的异质整合结构及其制作方法”, SIPO Patent CN 102263097, filed on Jul. 11, 2011, Issued Date: Nov. 30, 2011.
  72. 陈冠能, 林钟汉,“开关单元和开关单元阵列”, SIPO Patent CN 101304040 B, filed on May 5, 2008, Issued Date: Aug 11, 2010.
  73. D・m・纽恩斯, L・克鲁辛艾尔鲍姆, 金德起, 陈冠能, 朴炳柱, B・g・埃尔米格林, 林仲汉, C・科桑达拉曼, S・波卢索萨曼,“可编程相变材料结构及其形成方法”, SIPO Patent CN 101383337 B, filed on Jul. 31, 2008, Issued Date: Jul 21, 2010.
  74. 陈冠能, L・克鲁辛艾保姆, 丹尼斯・m・纽恩斯, 萨姆帕斯・普鲁肖萨曼,“可编程通孔器件及其制造方法和集成逻辑电路”, SIPO Patent CN 101359649, filed on Jul. 29, 2008, Issued Date: Jun 23, 2010.
  75. 陈冠能, L・克鲁辛艾保姆, 丹尼斯・m・纽恩斯, S・波卢索萨曼,“可编程通孔器件及其制造方法以及集成逻辑电路”, SIPO Patent CN 100590861 C, filed on Jul. 29, 2008, Issued Date: Feb 17, 2010.
  76. 陈冠能, 林仲汉,“半导体结构及其制造方法”, SIPO Patent CN 100567569 C, filed on Apr. 9, 2008, Issued Date: Dec 9, 2009.