Orbit

汪 大暉
姓名 汪 大暉
電子郵件 twang@cc.nctu.edu.tw
聯絡電話 (03)5712121 ext. 54143
個人網址 http://web.it.nctu.edu.tw/~dsml411/
簡介
 

  汪大暉教授畢業於國立台灣大學電機系,美國伊利諾大學香檳分校電機工程博士。 曾於美國HP實驗室(HP Labs)進行高速砷化鎵元件研發與蒙地卡羅模擬。研究領域包括快閃式記憶體元件, CMOS元件,高壓元件,奈米結構電荷傳輸理論分析等,目前擁有200多篇國際期刊與會議論文,及16項國際專利。

  汪教授曾擔任IEDM,IRPS,VLSI-TSA等多項國際學術會議技術委員並曾為IEEE IPFA 課程主席與台灣、香港、中國大陸之IEEE 電子元件Newsletter主編。並曾獲得教育部教學獎, IPFA最佳論文獎,並為2005 VLSI最佳學生論文獎之指導教授。

  汪教授目前擔任國際電子元件頂尖期刊 IEEE EDL編輯、旺宏電子顧問與交通大學教授。除此之外,並與工業界擁有多次合作,包括 加拿大NRC、工研院、台積電、聯電、旺宏、矽統、立錡等,都曾進行或正在進行多項研究計畫,計畫內容 涵蓋奈米級CMOS元件、Flash Memory、FinFET、Monte Carlo simulation、Strain CMOS、High K/ Metal Gate、高壓元件等。汪教授並曾擔任國家高普考典試委員。 

年度 論文名稱
2016 Y. L. Chou, Tahui Wang, Mercator Lin, Y. W. Chang, Lenvis Liu, S. W. Huang, W. J. Tsai, T. C. Lu, K. C. Chen, and Chih-Yuan Lu, Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String, IEEE Elect. Dev. Lett., Vol. 37, pp998-1001
2016 Yueh-Ting Chung, Po-Cheng Su, Wen-Jie Lin, Min-Cheng Chen, and Tahui Wang, SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory, IEEE Trans. on Elect. Dev., Vol. 63, pp2367-2373
2016 T. Wang, and C.C. Yu, Analysis of the DX Traps-induced Transient Characteristics in AlGaAs/GaAs HEMT’s, Solid-State Page 4 Electronics, Vol.33, pp1087-1090
2015 Yueh-Ting Chung, Po-Cheng Su, Yu-Hsuan Cheng, Tahui Wang, Min-Cheng Chen, and Chih-Yuan Lu, Cycling Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory, IEEE Elect. Dev. Lett., Vol.36, pp135-137
2013 J. P. Chiu, Y.H. Liu, H.D. Hsieh, C.W. Li, M.C. Chen and Tahui Wang, Statistical Characterization and Modeling of a Vt Distribution and Its Temporal Evolutions in NBTI Recovery, IEEE Trans. on Elect. Dev., Vol. 60, pp978-984
2012 J. P. Chiu, C. W. Li and Tahui Wang, Characterization and Modeling of Trap Number and Creation Time Distributions under Negative-Bias-Temperature Stress, Applied Phys. Lett., 082906, Vol. 101
2012 Y. T. Chung, T. I. Huang, C. W. Li, Y. L. Chou, J. P. Chiu, Tahui Wang, M. Y. Lee, K. C. Chen, C. Y. Lu, Vt Retention Distribution Tail in a Multi-Time-Program MLC SONOS Memory due to a Random Program Charge Induced Current-Path Percolation Effect, IEEE Trans. on Elect. Dev., Vol. 59, pp1371-1376,
2012 M.C. Chen, C.Y. Lin, B.Y. Chen, C.H. Lin, G.W. Huang, C.H. Ho, Tahui Wang, Chenming Hu, and F.L. Yang, Random Telegraph Noise in 1X nm CMOS Silicide Contacts and a Method to Extract Trap Density, IEEE Elect. Dev. Lett, Vol. 33, pp591-593
2012 J.P. Chiu, Y.T. Chung, Tahui Wang, M.C. Chen, C.Y. Lu, and K.F. Yu, A Comparative Study of NBTI and RTN Amplitude Distributions in High-k Gate Dielectric pMOSFETs, IEEE Elect. Dev. Lett., Vol. 33, pp176-178
2011 H.C. Ma, Y.L. Chou, J.P. Chiu, Y. T. Chung, T. Y. Lin, Tahui Wang, Y.P. Chao, K.C. Chen, and Chih-Yuan Lu,, A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory, IEEE Trans. on Elect. Dev., Vol. 58 , pp623-630
2011 Y.L. Chou, Y.T. Chung, Tahui Wang, S.H. Ku, N.K. Zou, Vincent Chen, W.P. Lu, K.C. Chen, and Chih-Yuan Lu, Variations of Vt Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect, IEEE Elect. Dev. Lett., 32, pp458-460
2009 Chun-Jung Tang, Tahui Wang, and Chih-Sheng Chang, Study of Quantum Confinement Effects on Hole Mobility in Silicon and Germanium Double Metal-Oxide-Semiconductor Field-Effect-Transistors, Applied Phys. Lett., 142103, Vol.95
2009 H.C. Ma, Y.L. Chou, J.P. Chiu, Tahui Wang, S.H. Ku, N.K. Zou, Vincent Chen, W.P. Lu, K.C. Chen, and Chih-Yuan Lu, Program Trapped Charge Effect on Random Telegraph Noise Amplitude in a Planar SONOS Flash Memory Cell, IEEE Elect. Dev. Lett., Vol.30, pp1188-1190
2009 Tahui Wang, Chun-Jung Tang, C.W. Li, C.H. Lee, T.F. Ou, Y.W. Chang, W.J. Tsai, T.C. Lu, K.C. Chen, and Chih-Yuan Lu, A Novel Hot Electron Programming Method in a Buried Diffusion Bit-line SONOS Memory by Utilizing Non-Equilibrium Charge Transport, IEEE Elect. Dev. Lett., vol. 30, pp165-167
2008 Tahui Wang, H.C. Ma, C.H. Li, Y.H. Lin, C.H. Chien and T.F. Lei, Charge Retention Loss in a HfO2 Dot Flash Memory via Thermally Assisted Tunneling, IEEE Elect. Dev. Lett., vol. 29, pp.109-110, pp109-110
2007 C.J. Tang, H.C. Ma , Tahui Wang, C.T. Chan, and C.S. Chang, Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs, IEEE Trans. on Device and Materials Reliability, vol. 7, pp518-523
2007 Y.Y. Liao, S.F. Horng, Y.W. Chang, T.C. Lu, K.C. Chen, Tahui Wang, and C.Y. Lu, Profiling of Nitride-Trap-Energy Distribution in SONOS Flash Memory by Using a Variable-Amplitude Low-Frequency Charge-Pumping Technique, IEEE Elect. Dev. Lett., pp828-830
2007 S.H. Gu, Tahui Wang, W.P. Lu, Y.H. Joseph Ku, and C.Y. Lu, Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells with Fowler-Nordheim Programming, IEEE Trans. Elect., Dev., pp90-97
2006 S.H. Gu, Tahui Wang, W.P. Lu, Y.H. Joseph Ku, and C.Y. Lu, Extraction of Nitride Trap Density from Stress Induced Leakage Current in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Flash Memory, Applied Phys. Lett., 163514, vol.89
2006 C. C. Cheng, J. F. Lin, Tahui Wang, T.H. Hsieh, J.T. Tzeng, Y.C. Jong, R.S. Liou, Samuel C. Pan, and S.L. Hsu, Physics and Characterization of Various Hot Carrier Degradation Modes in LDMOS by Using a Three-Region Charge Pumping Technique, IEEE Trans. on Device and Materials Reliability, pp358-363
2006 M.H. Lin, K.P. Chang, K.C. Su and Tahui Wang, Effects of Width Scaling and Layout Variation on Dual Damascene Copper Interconnect Electromigration, Microelectronics Reliability, pp2100-2108
2006 C. T. Chan, C. J. Tang, Tahui Wang, H. C.-H. Wang, and D. D. Tang, Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs, IEEE Trans. Elect., Dev., pp1340-1346
2006 W. J. Tsai, N. K. Zous, Tahui Wang, Ku, Y.-H.J., and C. Y. Lu, Novel Operation Method to Avoid Over-erasure in a Scaled Trapping-Nitride Localized Charge Storage Flash Memory Cell and Its Application for Multilevel Programming, IEEE Trans. Elect., Dev., pp808-814
2006 Tahui Wang, C. T. Chan, C. J. Tang, C. W. Tsai, H. C.-H. Wang, M. H. Chi, and D. D. Tang, Novel Transient Characterization Technique to Investigate Trap Properties in HfSiON Gate Dielectric MOSFETs–from Single Electron Emission to PBTI Recovery Transient, IEEE Trans. Elect., Dev., pp1073-1097
2006 S. H. Gu, Tahui Wang, W. P. Lu, W. Ting, Y. H. Joseph Ku, and C. Y. Lu, Characterization of Programmed Charge Lateral Distribution in a Two-bit Storage Nitride Flash Memory Cell by Using a Charge Pumping Technique, IEEE Trans. Elect., Dev., pp103-108
2006 M.H. Lin, K.P. Chang, K.C. Su, and Tahui Wang, Copper Interconnect Electro-migration Behavior in Various Structures and Precise Bimodal Fitting,, Japanese Journal of Applied Physics, pp700-709
2005 M. H. Lin, Y. L. Lin, J. M. Chen, M. S. Yeh, K. P. Chang, K. C. Su, and Tahui Wang, Electromigration Lifetime Improvement of Copper Interconnect by Cap/Dielectric Interface Treatment and Geometrical Design, IEEE Trans. Elect., Dev., pp2602-2608
2005 C. W. Tsai, S. C. Lai, C. T. Yen, H. M. Lien, H. L. Lung, T. B. Wu, Tahui Wang, Rich Liu, and C. Y. Lu, Mechanism for slow switching effect in advanced low-voltage, high-speed Pb(Zr1-xTix)O3 ferroelectric memory, IEEE Trans. on Device and Materials Reliability, pp217-223
2005 S. C. Chiang, M. F. Lu, S. H. Lu, S. C. Chien, and Tahui Wang, Substrate-bias-dependent dielectric breakdown in ultrathin-oxide p-metal-oxide-semiconductor field-effect transistors, J. Appl. Phys., p.24105, vol. 98
2005 J. W. Wu, J. W. You, H. C. Ma, C. C. Cheng, C. F. Hsu, C. S. Chang, G. W. Huang, Tahui Wang, Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling, IEEE Trans. Elect., Dev., pp2061-2066
2005 C. C. Yeh, Tahui Wang, W. J. Tsai, T. C. Lu, Y. Y. Liao, N. K. Zous, C. Y. Chin, Y. R. Chen, M. S. Chen, W. Ting, and C. Y. Lu, A novel fully CMOS process compatible PREM for SOC applications, IEEE Elect. Dev. Lett., pp203-204
2005 C. C. Yeh, Tahui Wang, W. J. Tsai, T. C. Lu, M. S. Chen, Y. Y. Liao, W. Ting, J. Ku, and C. Y. Lu, A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications, IEEE Trans. Elect., Dev., pp541-546
2005 M.H. Lin, and Tahui Wang, Copper Interconnect Electromigration Behavior in Various Structures and Lifetime Improvement by Cap/Dielectric Interface Treatment, Microelectronics Reliability, pp1061-1078
2004 J.W. Wu, J.W. You, H. C. Ma, C.C. Cheng, C.S. Chang, G.W. Huang, and Tahui Wang, Valence-Band Tunneling Induced Low Frequency Noise in Ultra-Thin Oxides (15A) n-type metal oxide semiconductor field effect transistors, Applied Phys. Lett., pp5076-5077
2004 M.C. Chen, S.H. Ku, C.T. Chan and Tahui Wang, Comparison of Oxide Breakdown Progression in Ultra-thin Oxide Silicon-On-Insulator and Bulk Metal-Oxide-Semiconductor Field Effect Transistors, J. Appl. Phys., pp3473-3477
2004 C. C. Yeh, Tahui Wang, W. J. Tsai, T. C. Lu, Y. Y. Liao, H. Y. Chen, N. K. Zous, W. Ting, J. Ku, and C. Y. Lu, A Novel Erase Scheme to Suppress Over Erasure in a Scaled 2-Bit Nitride Storage Flash Memory Cell, IEEE Elect. Dev. Lett., pp643-645
2004 N. K. Zous, M. Y. Lee, M. J. Tsai, A. Kuo, L. T. Huang, T. C. Lu, C. J. Liu, T. Wang, W. P. Lu, W. Ting, J. Ku, and C.Y. Lu, Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and its Qualification Methodology, IEEE Elect. Dev. Lett., pp649-651
2004 N. K. Zous, Y. J. Chen, C. Y. Chin, W. J. Tsai, T. C. Lu, M. S. Chen, W. P. Lu, T. Wang, S. C. Pan, C.Y. Lu, An Endurance Evaluation Method for Flash EEPROM, IEEE Trans. Elect., Dev., pp720-725
2004 J.W. Wu, J.C. Guo, K.L. Chiu, C.C. Cheng, W.Y. Lien, G.W. Huang and Tahui Wang, Pocket Implantation Effect on Drain Current Flicker Noise in Analog n-MOSFET Devices, IEEE Trans. Elect., Dev., pp1262-1266
2004 M.Y. Liu, Y.W. Chang, N.K. Zous, Ichen Yang, T.C. Lu, Tahui Wang, Wenchi Ting, Joseph Ku and C.Y. Lu, Temperature Effect on Read Current in a Two-Bit Nitride-Based Trapping Storage Flash EEPROM Cell, IEEE Elect. Dev. Lett., pp495-497
2004 M.C. Chen, S.H. Ku, C.T. Chan and Tahui Wang, Soft Breakdown Enhanced Hysteresis Effects in Ultra-thin Oxide Silicon-On-Insulator Metal-Oxide-Semiconductor Field Effect Transistors, J. Appl. Phys., vol. 41, pp2297-2300
2004 W. J. Tsai, C.C. Yeh, N.K. Zous, C.C. Liu, S. K. Cho, T. Wang, C. Y. Lu, Positive Oxide Charge Enhanced Read Disturb in a Localized Trapping Storage flash Memory Cell, IEEE Trans. Elect., Dev., pp434-439
2003 C.W. Tsai, M.C. Chen, S.H. Gu and Tahui Wang, Substrate Bias Dependence of Oxide Breakdown Progression in Ultra-thin Oxide pMOSFETs, IEEE Elect. Dev. Lett., pp296-271
2003 C.W. Tsai, M.C. Chen, S.H. Gu and Tahui Wang, Auger Recombination Enhanced Hot Carrier Degradation in nMOSFETs with a Forward Substrate Bias, IEEE Trans. Elect. Dev., pp1022-1026
2003 C. C. Yeh, T. H. Fan, T. C. Lu, Tahui Wang, Sam Pan and C. Y. Lu, A Novel Soft-Program for a Narrow Erased State Vt Distribution, Read Disturbance Suppression and Over-Program Annihilation in Multilevel Cell Flash Memories, Jpn. J. Appl. Phys., vol. 42, pp2044-2049
2002 Tahui Wang, N. K. Zous, C. C. Yeh, Role of Positive Trapped Charge in Stress-Induced Leakage Current for Flash EEPROM Devices, IEEE Trans. Elect. Dev, pp1910-1916
2002 H. Wang, C.C. Wang, C. Diaz, B.K. Liew, J.Y.C. Sun and T. Wang, Arsenic/Phosphorus LDD Optimization by Taking Advantage of Phosphorus Transient Enhanced Diffusion for High Voltage Input/Output CMOS Devices, IEEE Trans. on Elect. Dev., pp67-71
2002 D. Y. Lee, H. C. Lin, Tahui. Wang, et al, nhanced negative-bias-temperature instability of P-channel metal-oxide-semiconductor transistors due to plasma charging damage, JPN. J. Appl. Phys., vol41(4B), pp2419-2422
2001 H. Wang, C.C. Wang, C.S. Chang, T. Wang, P. Griffin and C. Diaz,, Interface Induced Up-Hill Diffusion of Boron: An Effective Approach for Ultra-Shallow Junction, IEEE Elect. Dev. Lett., vol. 22, pp55-67
2000 H. Wang, C. Diaz, B. K. Liew, J. Y. C. Sun and T. Wang, “Hot Carrier Reliability Improvement by Utilizing Phosphorus Transient Enhanced Diffusion for a Sub-0.25mm CMOS Technology,, IEEE Elect. Dev. Lett., vol. 21, pp589-600
1999 T. Wang, L. P. Chiang, N. K. Zous, C. F. Hsu, L. Y. Huang and T. S. Chao,, Comprehensive Study of Hot Carrier Stress Induced Drain Leakage Current Degradation in Thin-Oxide n-MOSFET's, Trans. on Elect. Dev., vol. 46, pp1877-1882
1999 N. K. Zous, T. Wang, C. C. Yeh and C. W. Tsai, Transient Effects of Positive Oxide Charge on Stress Induced Leakage Current in Tunnel Oxides, Appl. Phys. Lett., vol. 75, pp734-736
1999 B. C. Lin, Y. C. Chen, A. Chin, T. Wang and C. Tsai, The Deuterium Effect on Stress Induced Leakage Current, Jpn. J. Appl. Phys., vol. 38
1998 T. Wang, N. K. Zous, J. L. Lai and C. Huang, Hot Hole Stress Induced Leakage Current (SILC) Transient in Tunnel Oxides, IEEE Elect. Dev. Lett., Vol 19, pp411-413
1998 T. Wang, L. P. Chiang, N. K. Zous, T. E. Chang and C. Huang., Characterization of Various Stress-Induced Oxide Traps in MOSFET's by Using a Subthreshold Transient Current Technique, IEEE Trans. on Elect. Dev., Vol. 45, pp1791-1796
1998 T. Wang, T. E. Chang, L. P. Chiang, C. H. Wang, N. K. Zous and C. Huang, Investigation of Oxide Charge Trapping and Detrapping in a MOSFET by Using a GIDL Current Technique, IEEE Trans. on Elect. Dev., vol. 45, pp1511-1517
1997 L. P. Chiang, N. K. Zous, T. Wang, T. E. Chang, K. Y. Shen and C. Huang., Field and Temperature Effects on Oxide Charge Detrapping in a MOSFET by Measuring a Subthreshold Current Transient, Appl. Phys. Lett., Vo1, 71, pp1068-1070
1996 T. Wang, T. E. Chang, L. P. Chiang and C. Huang, A New Technique to Extract Oxide Trap Time Constants in MOSFET's, IEEE Elect. Dev. Lett., Vol. 17, pp398-400
1996 T. S. Liou, T. Wang and C. Y. Chang, Analysis of High-Field Hole Transport Characteristic in Si1-xGex Alloys with a Bond Orbital Band-Structure, J. of Appl. Phys., Vol. 79, pp259-263
1995 T. Wang, T. E. Chang, T. Y. Yang, K. M. Chang and L. P. Chiang., Structural Effect on Band-Trap-Band Tunneling Induced Drain Leakage in n-MOSFET's, IEEE Elect. Dev. Lett., Vol. EDL-16, pp566-568
1995 T. S. Liou, and T. Wang and C. Y. Chang, Calculation of the Structural Dependence of Infrared Absorption in P-type Strained Layer SiGe/Si Quantum Wells, J. of Appl. Phys., Vol. 77, pp6646-6650
1995 T. H. Hsich, H. Wang, T. Wang, T. H. Chen, Y. C. Chiang, S. T. Tseng, A. Chen and Y. Chang., An Ultra Low Cost and Miniature 950-2050MHz GaAs MMIC Downconverter-I: Design Approach and Simulation., Journal of Chinese Institute of Engineers, Vol. 18, pp437-444
1995 T. E. Chang, C. Huang and T. Wang., Mechanisms of Interface Trap Induced Drain Leakage Current in OFF-State n-MOSFET's, IEEE Trans. on Elect. Dev., Vol. 42, pp738-743
1995 C. Huang, T. Wang., Transient Simulation of EPROM Writing Characteristics with a Novel Hot Electron Injection Model, Solid-State Electronics, Vol. 38, pp461-464
1994 T. Wang, C. Huang, T. E. Chang, J. W. Chou and C. Y. Chang., Interface Trap Effect on Gate Induced Drain Leakage Current in Submicron MOSFET's, IEEE Trans. on Elect. Dev., Vol. 41, pp2475-2477
1994 T. Wang, C. Huang, P. C. Chou, S. S. Chung and T. E. Chang, "Effects of Hot Carrier Induced Interface State Generation in Submicron LDD MOSFET's, IEEE Trans. on Elect. Dev., Vol. 41, pp1618-1622
1994 T. S. Liou, T. Wang, and C. Y. Chang., Calculation of Hole Mobility in Doped SiGe Alloys Using a Monte Carlo Method with a Band Orbital Band-Structure,, J. of Appl. Phys., Vol. 76, pp4749-4752
1993 T. Wang, T. H. Hsieh, T. W. Chen, Quantum confinement effects on low-dimensional electron-mobility, J. Appl. Phys. , Vol.74 (1), pp426-430
1993 Tahui Wang; Sheng-Jyh Wu; Chimoon Huang,, Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters, Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp1758-1761
1992 T. Wang, T. H. Hsieh, and Y. T. Chen,, Quantum Well Geometrical Effects on Two Dimensional Electron Mobility, Solid-State Electronics, Vol.35, pp1597-1599
1992 Chimoon Huang; Tahui Wang; Chen, C.N.; Chang, M.C.; Fu, J., Modeling hot-electron gate current in Si MOSFET's using a coupled drift-diffusion and Monte Carlo method, IEEE Trans. on Elect. Dev., Vol. 39, pp2562-2568
1991 Tahui Wang, Mixed-mode simulation of DX trap-induced slow transient effects on AlGaAs/GaAs HEMT inverters, IEEE Trans. on Elect. Dev., Vol. 38, pp1993-1998
1990 Tahui Wang; Cheng-Hsiang Hsieh, Numerical analysis of nonequilibrium electron transport in AlGaAs/InGaAs/GaAs pseudomorphic MODFETs, IEEE Trans. on Elect. Dev., Vol. 37, pp1930-1938
1986 T. Wang, K. Hess and G.J. Iafrate, Monte Carlo Simulation of Hot Electron Spectroscopy in Planar-Doped Barrier Transistor, J. Appl. Phys., Vol.59, pp2125-2128
1986 T. Wang, J.P. Leburton, K Hess, D. Bailey., Absence of Spatial Coherence Effects of Carrier Energy and Velocity in GaAs-AlGaAs-GaAs Tunnel Structures,, Physical Review B, Vol. 33, pp2906-2908
1985 V. Robbins, K. Brennan, T. Wang, K. Hess, G.. Stillman, Experimental Determination of Impact Ionization Rates in Si, J. Appl. Phys., Vol.58, pp4614-4617
1985 T. Wang, K. Hess, Calculation of the Electron Velocity Distribution in High Electron Mobility Transistor Using an Ensemble Monte Carlo Method, J. Appl. Phys., Vol.57, pp5336-5339
1985 K. Brennan, T. Wang, K. Hess,, Theory of Electron Impact Ionization Including a Potential Step: Application to GaAs-AlGaAs, IEEE Elect. Dev Lett., EDL-6, pp199-201
1985 T. Wang, K. Hess, G.J. Iafrate., Time-Dependent Ensemble Monte Carlo Simulation for Planar-Doped GaAs structure, J. Appl. Phys., Vol.58, pp857-861
1984 T. Wang, K. Hess., Caculation of High-Field Diffusivity by a Many-Particle Monte Carlo Simulation Including a Complete Band Structure for GaAs, J. Appl. Phys., Vol.56, pp2793-2795
1982 T.J. Drummond, T. Wang, W. Kopp, H. Mockoc, R. Thorne, S.L. Su, A Novel Normally-Off Camel Diode Gate GaAs Field –Effect Transistor, Appl. Phys. Lett., Vol. 40, pp834-836
1982 W. Kopp, T.J. Drummond, T. Wang, H. Mockoc, S.L. Su, A Novel Camel Diode Gate GaAs FET, Elect. Dev Lett., EDL-3, pp86-88
年度 論文名稱
2016 P. C. Su, Y. T. Chung, M. C. Chen, and Tahui Wang., Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory, 2016 IEEE 8th International Memory Workshop (IMW), Paris, France
2015 M.C. Chen, K.S. Li, L.J. Li, A.Y. Lu, M.Y. Li, Y.H. Chang, C.H. Lin, Y.J. Chen, Y.F. Hou, C.C. Chen, B.W. Wu, C.S. Wu, Ivy Yang, Y.J. Lee, J.M. Shieh, W.K. Yeh, J.H. Shih, P.C. Su, A.B. Sachid, Tahui Wang, F.L. Yang and Chenming Hu., TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology, IEEE International Electron Devices Meeting(IEDM), Washington
2014 .ChY. T.Chung.Y.H. Liu,P.C.Su, Y.H.Cheng,T.Wang,and M.C.Chen, investigation of random telegraph noise amplitudes in hafnium oxide resistive memory devices, IEEE International Reliability Physics Symposium (IRPS), Hawaii, USA
2014 M. C. Chen, C. Y. Lin, K. H. Li, L. J. Li, C. H. Chen, C. H. Chuang, M. D. Lee, Y. J. Chen, Y. F. Hou, C. H. Lin, C. C. Chen, B. W. Wu, C. S. Wu, I. Yang, Y. J. Lee, W. K. Yeh, T. Wang and F. L. Yang., Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for Vth Matching and CMOS-Compatible 3DFETs, IEEE International Electron Device Meeting(IEDM), San Francisco
2014 C. H. Lin, M. C. Chen, Y. F. Hou, Y. H. Lin, J. Y. Hsu, Y. H. Cheng, P.C. Su, Y. J. Chen, C. Y. Lin, K.H. Li, M.T.Lee, C.A. Chung, W. K. Yeh, and T. Wang, A Reliable Tantalum Oxide-based ReRAM with Ultralow Voltage Switching for Fully CMOS-compatible 1T1R Integration, IEEE Semiconductor Interface Specialists Conferences (SISC), San Diego
2013 M.C. Chen, Chen, C.H. Lin, Y.F. Hou, Y.J. Chen, C.Y. Lin, F.K. Hsueh, H.L. Liu, C.T. Liu, B.W. Wang, H.C. Chen, C.C. Chen, S.H. Chen, C.T. Wu, T.Y. Lai, M.Y. Lee, B.W. Wu, C.S. Wu, I. Yang, Y.P. Hsieh, C.H. Ho, Tahui Wang, A B. Sachid, Chenming Hu, and Fu-Liang Yang,, A 10 nm Si-based Bulk FinFETs 6T SRAM with Multiple Fin Heights Technology for 25% Better Static Noise Margin, International Symp. on VLSI Tech. (VLSI), Kyoto, Japan,
2013 M.C. Chen, H.C. Chen, T.H. Lee, Y.H. Lin, C.H. Shin, B.W. Wang, Y.F. Hou, Y.J. Chen, C.Y. Lin, C.H. Lin, C.H. Ho, M.Y. Hua. J. T. Qiu, Tahui Wang, Fu-Liang Yang., Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode, Int. Reliability Phys. Symp. (IRPS)
2011 M.C. Chen, C.Y. Lin, B.Y. Chen, C.H. Lin, G.W. Huang, C.C. Huang, C.H. Ho, Tahui Wang, Chenming Hu, and F.L. Yang,, Silicide Barrier Engineering Induced Random Telegraph Noise in 1X nm CMOS Contacts, IEEE International Electron Device Meeting(IEDM)
2011 Chien-Ying Lee, C.H. Lee, C.H. Cheng, J.S. Huang, S.H. Ku, N.K. Zous, K.C. Chen, Tahui Wang and Chih-Yuan Lu, Characterization of Junction Dosage Effect on NAND Arrays by Using Charge Pumping Method,, VLSI-TSA
2011 C.H. Lee, I.C. Yang, C.Y. Lee, C.H. Cheng, S.H. Ku, N.K. Zous, W.P. Lu, K.C. Chen, Tahui Wang, Chih-Yuan Lu,, Optimization for Reliability Issues in Floating Gate NAND Flash Cells, Int. Reliability Phys. Symp. (IRPS)
2010 T.H. Yeh, S.W. Lin, Y.J. Chen, K.F. Chen, J.S. Huang, S.H. Ku, N.K. Zous, W.P. Lu, K.C. Chen, Tahui Wang and Chih-Yuan Lu., Gate Stack Etch Induced Reliability Issues in Nitride-Based Trapping Storage Cells, VLSI-TSA
2010 Y.L. Chou, J.P. Chiu, H.C. Ma, Tahui Wang, Y.P. Chao, K.C. Chen, and Chih-Yuan Lu, Use of Random Telegraph Signal as Internal Probe to Study Program/Erase Charge Lateral Spread in a SONOS Flash Memory, Int. Reliability Phys. Symp. (IRPS)
2010 T. Wang,, Random Telegraph Noise and Scaling Concerns in SONOS Flash Memory, Symposium on Nano Device Technology(SNDT)
2009 C.H. Lee, W.H. Tu, L. H. Chong, S.H. Gu, K.F. Chen, Y.J. Chen, J.Y. Hsieh, I.J. Huang, N.K. Zous, T.T. Han, M.S. Chen, W.P. Lu, K.C. Chen, Tahui Wang and C.Y. Lu,, Overall Operation Considerations for a SONOS-based Memory, VLSI-TSA
2009 H.C. Ma, J.P. Chiu, C.J. Tang and Tahui Wang,, Investigation of Post-NBT Stress Current Instability Modes in HfSiON Gate Dielectric pMOSFETs by Measurement of Individual Trapped Charge Emissions, Int. Reliability Phys. Symp. (IRPS)
2009 J.P. Chiu, Y.L. Chou, H.C. Ma, Tahui Wang, S.H. Ku, N.K. Zou, Vincent Chen, W.P. Lu, K.C. Chen, and Chih-Yuan Lu,, Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory, IEEE International Electron Device Meeting(IEDM)
2009 C.H. Lee, W.H. Tu, S.H. Gu, C.W. Wu, S.W. Lin, T.H. Yeh, K.F. Chen, Y.J. Chen, J.Y. Hsieh, I.J. Huang, N.K. Zous, T.T. Han, M.S. Chen, W.P. Lu, K.C. Chen, Tahui Wang and C.Y. Lu., Cell Endurance Prediction from a Large-area SONOS Capacitor, Int. Reliability Phys. Symp. (IRPS)
2008 Tahui Wang,, Reliability Issues in NOR-Type SONOS Flash Memory Scaling, NSC-JST Nano Device Workshop
2008 W.J. Tsai, T.F. Ou, J.S. Huang, C.H. Cheng, C.Y. Lu, Tahui Wang, T.C. Lu, K.C. Cheng, and C.Y. Lu,, Highly Punchthrough-Immune Operation Method for An Ultra-Short-Channel Hot-Carrier-Injection Type Non-Volatile Memory Cell, IEEE International Electron Device Meeting(IEDM), San Francisco, U.S.A.
2008 C.H. Lee, C.W. Wu, S.W. Lin, T.H. Yeh, S.H. Gu, K.F. Chen, Y.J. Chen, J.Y. Hsieh, I.J. Huang, N.K. Zous, T.T. Han, M.S. Chen, W.P. Lu, Tahui Wang, and C.Y. Lu., Numerical Simulation of Programming Transient Behavior in Charge Trapping Storage Memory, Non-Volatile Semiconductor Memory Workshop(NVSM),
2008 C.H. Lee, C.W. Wu, S.W. Lin, T.H. Yeh, S.H. Gu, K.F. Chen, Y.J. Chen, J. Y. Hsieh, I.J. Huang, N. K. Zous, T.T. Han, M.S. Chen, W.P. Lu, K.C. Chen, T. Wang and C.Y. Lu,, Numerical Simulation of the Read Disturb Behavior on the ONO Scaling Margin in SONOS Flash Memory, International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan,
2007 C.J. Tang, S.H. Huang, Tahui Wang, and C.S. Chang, Investigation of the Strained PMOS on (110) Substrate, VLSI-TSA
2007 C.C. Cheng, J.F. Lin, Tahui Wang, T.H. Hsieh, J.T. Tzeng, Y.C. Jong, R.S. Liou, Samuel C. Pan, and S.L. Hsu, Impact of Self-Heating Effect on Hot Carrier Degradation in High-Voltage LDMOS, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.,
2007 C.J. Tang, C.W. Li, Tahui Wang, S.H. Gu, P.C. Chen, Y.W. Chang, T.C. Lu, W.P. Lu, K.C. Chen, and C.Y. Lu., Characterization and Monte Carlo Analysis of Secondary Electrons Induced Program Disturb in a Buried Diffusion Bit-line SONOS Flash Memory, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2006 C.C. Yeh, Tahui Wang, W.J. Tsai, T.C. Lu, Y.Y. Liao, T.F. Ou, M.S. Chen, Y.J. Chen, E.K. Lai, Y.H. Shih, W.C. Ting, J. Ku, and C.Y. Lu, Insight of stress effect on the ONO stack layer in a SONOS-type flash memory cell, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2006 Tahui Wang,, Nitride Trap Storage Flash Memory – Reliability of Scaling Issues, Symposium on Nano Device Technology(SNDT)
2006 M.H. Lin, and Tahui Wang,, Effects of width scaling, length scaling, and layout variation on electron-migration in dual damascene copper interconnects, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2006 W.J. Tsai, Tahui Wang, W.C. Ting, J. Ku, and C.Y. Lu, Investigation of Charge Loss in Cycled NBit Cells via Field and Temperature Accelerations, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2006 W.J. Tsai, T.F. Ou, H.L. Kao, E.K. Lai, Y.Y. Liao, C.C. Yeh, Tahui Wang, J. Ku, and C. Y. Lu,, A Novel Non-Volatile Memory Cell Using a Gated-Diode Structure with a Trapping-Nitride Storage Layer, nternational Symp. on VLSI Tech. (VLSI), Hawaii, USA
2006 S.H. Gu, C.W. Li, Tahui Wang, W.P. Lu, K.C. Chen, Joseph Ku, and C.Y. Lu., Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory, IEEE International Electron Device Meeting(IEDM), San Francisco, USA
2006 C.J. Tang, H.C. Ma, C.T. Chan, Tahui Wang, and H. C.-H. Wang, NBT Stress Induced Anomalous Drain Current Instability in HfSiON pMOSFETs Arising from Bipolar Charge Trapping, International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan
2006 C.C. Cheng, K.C. Tu, Tahui Wang, T.H. Hsieh, J.T. Tzeng, Y.C. Jong, R.S. Liou, Sam C. Pan, and S.L. Hsu, Investigation of Hot Carrier Degradation Modes in LDMOS by Using a Novel Three-Region Charge Pumping Technique, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2005 C. T. Chan, H.C. Ma, C.J. Tang, and Tahui Wang, Investigation of Post-NBTI Stress Recovery in pMOSFETs by Direct Measurement of Single Oxide Charge De-Trapping, International Symp. on VLSI Tech. (VLSI), Kyoto, Japan
2005 M. H. Lin, K. P. Chang, K. C. Su and Tahui Wang, Width Scaling and Layout Variation Effects on Dual Damascene Copper Interconnects Electromigration,, International Conference on Solid State Devices and Materials (SSDM), Japan
2005 C. T. Chan, C. J. Tang, Tahui Wang, H. C.-H. Wang, and D. D. Tang, Positive Bias and Temperature Stress Induced Two-Stage Drain Current Degradation in HfSiON nMOSFET's,, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2005 C. T. Chan, C. J. Tang, C. H. Kuo, C.W. Tsai, H.C.-H. Wang, M. H. Chi, and Tahui Wang, Single-electron Emission of Traps in HfSiON as High-k Gate Dielectric for MOSFETs, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2005 J.W. Wu, H.C. Ma, C.C. Cheng, G.W. Huang, C.S. Chang, and Tahui Wang, Low Frequency Noise Degradation in Ultra-Thin Oxide (15A) Analog n-MOSFETs Resulting from Valence-Band Tunneling, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2005 C. C. Yeh, Tahui Wang, Y. R. Chen, F. M. Pan, S. H. Gu, W. J. Tsai, T. C. Lu, Y. Y. Liao, W. C. Ting, J. Ku, and C. Y. Lu,, A Novel Silicon-Nitride Based Light-Emitting Transistor (SiNLET): Optical / Electrical Properties of a SONOS-Type Three-Terminal Electroluminescence Device for Optical Communication in ULSI, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2005 C.C. Yeh, Tahui Wang, Y.Y. Liao, W.J. Tsai, T.C. Lu, M.S. Chen, Y.R. Chen, K.F. Chen, Z.T. Han, M.S. Wong, S.M. Hsu, N.K. Zous, T.F. Ou, W.C. Ting, J. Ku, and C.-Y. Lu,, A Novel NAND-Type PHINES Nitride Trapping Storage Flash Memory Cell With Physically 2-bits- Per-Cell Storage, and a High Programming Throughput for Mass Storage Applications, International Symp. on VLSI Tech. (VLSI), Kyoto, Japan
2005 S. Chiang, M.C. Chen, W.S. Liao, J.W. You, M.F. Lu, Y.S. Hsieh, W.M. Lin, S. Huang-Lu , W.T. Shiau, S.C. Chien, and Tahui Wang, Channel Soft Breakdown Enhanced Excess Low-Frequency Noise in Ultra-Thin Gate Oxide PD Analog SOI Devices,, Int. Reliability Phys. Symp. (IRPS), San Jose, U.S.A.
2004 M.Y. Lee, N.K. Zous, T. Huang, W.J. Tsai, A. Kuo, Tahui Wang, S. Yin, and C. Y. Lu,, A Temperature Accelerated Model for High State Retention Loss of Nitride Storage Flash Memory, IEEE Int. Integrated Reliability Workshop (IRW)
2004 J.W. Wu, J.W. You, H. C. Ma, C.C. Cheng, G.W. Huang, C.S. Chang, and Tahui Wang, Valence-Band Tunneling Induced Low Frequency Noise in Ultra-Thin Oxides (15A) Analog n-MOSETs, Int. Electron Devices and Materials Symposium (IEDMS), Hsinchu, Taiwan
2004 C. C. Cheng, J. W. Wu, C. C. Lee, J. H. Shao and, Tahui Wang,, Hot Carrier Degradation in LDMOS Power Transistors, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 M.F. Lu, M.C. Chen, Alex Liu, M.S. Yeh, J. R. Hwang and Howard Tang, W.T. Shiau, S.W. Sun, Tahui Wang,, Hot Carrier Degradation in Novel Strained-Si nMOSFETs, Int. Reliability Phys. Symp. (IRPS), Phoenix, U.S.A.
2004 M. H. Lin, T. Wang, et al., The Improvement of Copper Interconnect Electromigration Resistance by Cap/Dielectric Interface Treatment and Geometrical Design, Int. Reliability Phys. Symp. (IRPS), Phoenix, U.S.A.,
2004 H. C. Cheng, C. C. Lin, T. Y. Hsiao, J. T. Wu, and T. Wang,, Multi-level Memory System Using Error Control Code, Int. Symp. on Circuit And System (ISCAS)
2004 C. T. Chan, C. H. Kuo, C. J. Tang, M. C. Chen, Tahui Wang, S. Huang Lu, H. C. Hu, T. F. Chen, C. K. Yang, M. T. Lee, D. Y. Wu, J. K. Chen, S. C. Chien and S. W. Sun, Comparison of Oxide Breakdown Progression in Ultra-Thin Oxide SOI and Bulk pMOSFETs, European Symposium Reliability of Electron Devices, Failure Physics and Analysis (ESREF),, Zurich, Switzerland
2004 W.J. Tsai, C.C. Yeh, C.C. Liu, C.J. Hwang, Y.C. Chen, T. Liang, A. Liu, R.B. Chang, N.K. Zous, M.I. Liu, Tahui Wang, W. Ting, J. Ku, and C.Y. Lu, Novel PHINES Flash EEPROM with 0.046m2 Bit Size for Giga-bit Era Application, Non-Volatile Semiconductor Memory Workshop(NVSM)
2004 C. T. Chan, C. H. Kuo, C. J. Tang, M. C. Chen, Tahui Wang, S. Huang Lu, H. C. Hu, T. F. Chen, C. K. Yang, M. T. Lee, D. Y. Wu, J. K. Chen, S. C. Chien and S. W. Sun, Floating Body Accelerated Breakdown Progression in Ultra-Thin Oxide PD SOI pMOSFETs, International Conference on Solid State Devices and Materials (SSDM),, Tokyo, Japan
2004 C. T. Chan, C. H. Kuo, C. J. Tang, M. C. Chen, Tahui Wang, S. Huang Lu, H. C. Hu, T. F. Chen, C. K. Yang, M. T. Lee, D. Y. Wu, J. K. Chen, S. C. Chien and S. W. Sun, Comparison of Oxide Breakdown Progression in Ultra-Thin Oxide SOI and Bulk pMOSFETs, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 N.K. Zous, Y.J. Chen, C.Y. Chin, W.J. Tsai, T.C. Lu, M.S. Chen, W.P. Lu, Tahui Wang, S.C. Pan, J. Ku, and C.Y. Lu, Relationship between AC Stress and DC Stress on Tunnel Oxides, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 S.C. Lai, C.W. Tsai, C.T. Yen, C.L. Liu, S.Y. Lee, H.M. Lien, S.L. Lung, C.H. Chien, T.B. Wu, Tahui Wang, R. Liu, and C.Y. Lu, “Mechanism for Slow Programming in Advanced Low-Voltage, High-Speed Ferroelectric Memory, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 M.H. Lin, Y.L. Lin, G.S. Yang, M.S. Yeh, K.P. Chang, K.C. Su, and Tahui Wang, Comparison of Copper Interconnect Electromigration Behaviors in Various Structures for Advanced BEOL Technology, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 C.C. Yeh, W.J. Tsai, T.C. Lu, Y.Y. Liao, N.K. Zous, H.Y. Chen, Tahui Wang, W. Ting, J. Ku, and C.Y. Lu, Reliability and Device Scaling Challenges of Trapping Charge Flash Memories, Int. Phys. and Failure Analysis of Integrated Circuit (IPFA), Hsinchu, Taiwan
2004 S.H. Gu, M.T. Wang, C.T. Chan, N.K. Zous, C.C. Yeh, W.J. Tsai, T.C. Lu, Tahui Wang, Joseph Ku, and Chih-Yuan Lu,, Investigation of Programmed Charge Lateral Spread in a Two-bit Nitride Storage Flash Memory Cell by Using a Charge Pumping Technique, Int. Reliability Phys. Symp. (IRPS), Phoenix, U.S.A.,
2004 W.J. Tsai, N.K. Zous, M.H. Chou, Smile Huang, H.Y. Chen, Y.H. Yeh, M.I. Liu, C.C. Yeh, T. Wang, Sam Pan, and Chih-Yuan Lu, Cause of Erase Speed Degradation During Two-Bit Per Cell Operation of a Trapping Nitride Storage Flash Memory Cell,, Int. Reliability Phys. Symp. (IRPS), Phoenix, U.S.A.
2003 C. C. Yeh, T. C. Lu, W. J. Tsai, T. Wang, W. Ting, J. Ku, C. Y. Lu, Challenges of Trapping Charge Flash Memory: SONOS, Nbit/NROM, and PHINES toward Gigabit and Nanotechnology Era, Int. Symp. On Advanced Devices and Process, Tokyo, Japan
2003 Lai, H.C.; Zous, N.K.; Tsai, W.J.; Lu, T.C.; Tahui Wang; King, Y.C.; Pan, S., Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFET's, Microelectronic Test Structures,
2003 Tahui Wang, W.J. Tsai, S.H. Gu, C.T. Chan, C.C. Yeh, N.K. Zous, T.C. Lu, Sam Pan, and C.Y. Lu,, Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2003 Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory, NROM Reliability Physics and Qualification Methodology, Infineon, Dresden Germany,
2003 C. C. Yeh, W. J. Tsai, S. K. Cho, Tahui Wang, Sam Pan, Chih-Yuan Liu, A Modified Read Scheme to Improve Read Disturb and Second Bit Effects in a Scaled MXVAND Flash Memory Cell, Non-Volatile Semiconductor Memory Workshop(NVSM)
2003 T. Wang, C.W. Tsai, M.C. Chen, C.T. Chan and H.K. Chiang, Negative Substrate Bias Enhanced Breakdown Hardness in Ultra-Thin Oxide pMOSFETs, Int. Reliability Phys. Symp. (IRPS), Dallas,
2003 C. C. Yeh, W.J. Tsai, T.C. Lu, H.Y. Chen, H.C. Lai, N.K. Zous, Y.Y. Liao , G.D. You, S.K. Cho, C.C. Liu, F.S. Hsu, L.T. Huang, W.S. Chiang, C.J. Liu, C.F. Cheng, M.H. Chou, C.H. Chen, T. Wang, Wenchi Ting, Sam Pan, Joseph Ku, and Chih-Yuan Lu,, Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2003 Jun-Wei Wu, J.C. Guo, Kai-Lin Chiu, Chih-Chang Cheng , W.Y. Lien, G.W. Huang and Tahui Wang, “Modeling of Pocket Implant Effect on Drain Current Flicker Noise in High Performance Analog CMOS Devices, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
2003 Da-Yuan Lee, Horng-Chih Lin, Chi-Chun Chen, Chao-Hsin Chien, Tiao-Yuan Huang, Tahui Wang, Tze-Liang Lee, Shih-Chang Chen, and Mong-Song Liang., New Mechanism for Negative-Bias-Temperature Instability and Its Impact on Scaling of pMOSFETs, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
2003 Da-Yuan Lee; Horng-Chih Lin; Chia-Lin Chen; Tiao-Yuan Huang; Tahui Wang; Tze-Liang Lee; Shih-Chang Chen; Mong-Song Liang;, Impacts of HF etching on ultra-thin core gate oxide integrity in dual gate oxide CMOS technology, Plasma- and Process-Induced Damage (PPID)
2002 J. W. Wu, H. C. Chang and T. Wang, Oxide Soft Breakdown effects on Drain Current flicker Noise in Ultra-Thin Oxide CMOS Devices, International Conference on Solid State Devices and Materials (SSDM)
2002 C. C. Yeh, W. J. Tsai, M. I. Liu, T. C. Lu, S. K. Cho, C. J. Lin, Tahui Wang, Sam Pan, and Chih-Yuan Lu, PHINES: A Novel Low Power Program/Erase, Small Pitch , 2-Bit per Cell Flash Memory, IEEE International Electron Device Meeting(IEDM)
2002 J. W. Wu, C. C. Lee, and Tahui. Wang,, The Comparison of hot Carrier Reliability in N-LDMOS and P-LDMOS Transistors, International Electronic Devices and Materials Symposiums (EDMS), Taipei, Taiwan
2002 Da-Yuan Lee; Horng-Chih Lin; Wan-Ju Chiang; Wen-Tai La; Nuang, G.; Tiao-Yuan Huang; Tahui Wang, Process and doping species dependence of negative-bias-temperature instability for P-channel MOSFETs, Plasma- and Process-Induced Damage (PPID)
2002 W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu,, Cause of Data Retention Loss in Nitride-Based Localized Trapping Storage Flash Memory Cells, Int. Reliability Phys. Symp. (IRPS), Dallas,U.S.A
2002 M. C. Chen, C. W. Tsai, S. H. Gu, T. Wang, S. Huang Lu, E. Lin, S. C. Chien, Y. T. Loh and F. T. Liu, Soft Breakdown Enhanced Hysteresis Effects in Ultra-Thin Oxide SOI nMOSFETs,”, Int. Reliability Phys. Symp. (IRPS), Dallas,U.S.A
2002 M. H. Lin, G. S. Yang, Y. L. Lin, M. T. Lin, C. C. Lin, M. S. Yeh, K. P. Chang, K. C. Su, J. K. Chen, Y. J. Chang, Tahui Wang,, A Practical Methodology for Multi-Modality Electromigration Lifetime Prediction, IEEE International Integrated Reliability Workshop (IRW),
2002 D. Y. Lee, H. C. Lin, M.Y. Tsai, W. J. Chiang, W. T. Lu, G. W. Huang, T. Y. Huang, and T. Wang, Effects of Process Treatments on Negative-bias-Temperature Instability of P-Channel MOSFETS, Int. Electron Devices and Materials Symposium (IEDMS), Taipei, Taiwan
2001 T. Wang, C.W. Tsai, and M.C. Chen,, Auger Recombination Enhanced Hot Carrier Effects and Luminescence in MOSFETs, 2001 NSC-NRC Workshop on Nano and Nano Electronics, Ottawa, Canada,
2001 W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu and S. H. Gu,, Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2001 D.Y. Lee, H.C. Lin, M.Y. Tsai, T.Y. Huang and T. Wang,, Post-Soft-Breakdown Characteristics of Deep Sub-Micron nNOSFETs with Ultra-Thin Gate Oxide, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
2001 T. Wang,, Flash Memory Reliability and R&D Trend, Macronix 2001 VLSI Technology Workshop, Hsin-Chu, Taiwan
2001 H. C. Lin, D. Y. Lee, C. Y. Lee, T. S. Chao, T. Y. Huang, and T. Wang,, New Insight into Breakdown Modes and Their Evolution in Ultra-Thin Gate Oxide,, VLSI-TSA, Hsinchu, Taiwan
2001 D.Y. Lee, H.C. Lin, M.F. Wang, M.Y. Tsai, T.Y. Huang and T. Wang,, Enhanced Negative-Bias-Temperature Instability of P-Channel MOSFET by Plasma Charging Damage, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
2001 C.W. Tsai, S.Y. Lee, S.L. Lung and T. Wang, Modeling of Polarization Relaxation Effects in Ferroelectric Memory, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
2001 S. L. Lung, C. L. Liu, S. S. Chen, S. C. Chen, S. C. Lai, C. W. Tsai, T. T. Sheng, T. Wang, S. Pan, T. B. Wu and R. Liu, Low Temperature Epitaxial Growth of PZT on Conductive Perovskite LaNiO3 Electrode for Embedded Capacitor-Over Interconnect (COI) FeRAM Application, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2001 H. Wang, C.C. Wang, C.H. Hsieh, S.Y. Lu, M. C. Chiang, Y. L. Chu, C. J. Chen, T. C. Ong, T. Wang, P. Griffin and C. Diaz,, Antimony Assisted Arsenic S/D Extension (A3 SDE) Engineering for Sub-0.1μm nMOSFET’s: A Novel Approach to Steep and Retrograde Indium Pocket Profiles, IEEE International Electron Device Meeting(IEDM), Washington DC, U.S.A.
2000 M. C. Chen, C. W. Wu, C. W. Tsai, T. Wang, Y. C. Liu, L. S. Huang, M. C. Wang and L. C. Hsia,, Stress Induced Gate-Width Edge Effects in STI pMOSFET’s, Int. Electron Devices and Materials Symposium (IEDMS), Chung-Li, Taiwan
2000 N. K. Zous, L. P. Chiang, C. W. Tsai and T. Wang, Auger Recombination Enhanced Hot Electron Programming in Flash EEPROMs, International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan
2000 C. W. Tsai, S. H. Gu, L. P. Chiang, T. Wang, Y. C. Liu, L. S. Huang, M. C. Wang and L. C. Hsia, Valence-Band Tunneling Enhanced Hot Carrier Degradation in Ultra-Thin Oxide nMOSFETs, IEEE International Electron Device Meeting(IEDM), San Francisco, USA
2000 N. K. Zous, L. P. Chiang, C. C. Yeh and T. Wang, Simulation of Positive Oxide Trapped Charge Induced Leakage Current and Read-Disturb in Flash EEPROMs, International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan
2000 L. P. Chiang, C. W. Tsai, T. Wang, U. C. Liu, M. C. Wang and L. C. Hsia, Auger Recombination Enhanced Hot Carrier Degradation in nMOSFETs with Positive Substrate Bias, International Symp. on VLSI Tech. (VLSI), Hawaii, USA
2000 K. Ramanujaachar, D. Landheer, S. Raymond, S. N. Charbonneau, P. Coleridge and T. Wang, Picosecond Imaging of Hot Electron Emission from CMOS Circuitry, Proc. SPIE,, Taiwan.
1999 L. P. Chiang, L. Y. Huang, N. K. Zous and T. Wang,, Stress Induced Subthreshold Current Hump in Short Gate-Length pMOSFETs with Shallow Trench Isolation,”, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan
1999 N. K. Zous, C. C. Yeh, C. W. Tsai, L. P. Chiang and T. Wang, Edge FN Stress Induced Leakage Current in Tunnel Oxides, VLSI-TSA, Taipei, Taiwan.
1999 T. Wang,, Hot Carrier Reliability Simulation in Flash EEPROM devices, NHPC-TCAD, Hsin-Chu, Taiwan
1999 N. K. Zous, T. Wang, C. C. Yeh, C. W. Tsai and C. Huang, A Comparative Study of SILC Transient Characteristics and Mechanisms in FN Stressed and Hot Hole Stressed Tunnel Oxides, Int. Reliability Phys. Symp. (IRPS), San Diego, U.S.A.
1999 T. Wang, C. F. Hsu, L. P. Chiang, N. K. Zous, C. Y. Chang and T. S. Chao., Voltage Scaling and Temperature Effects on Drain leakage Current Degradation in a Hot Carrier Stressed n-MOSFET, Int. Reliability Phys. Symp. (IRPS), Reno, U.S.A.
1998 T. Wang, Some Reliability Issues in Flash EEPROM Devices,, 3rd Photonics and Semiconductor Device Reliability Workshop, Hsin-Chu, Taiwan
1998 B. C. Lin, Y. C. Cheng, A. Chin, T. Wang and C. Tsai, The Deuterium Effect on SILC, International Conference on Solid State Devices and Materials (SSDM), Hiroshima, Japan
1998 T. Wang, N. K. Zous, L. Y. Huang, C. K. Yeh and T. S. Chao, Oxide Thickness Dependence of Hot Carrier Stress Induced Drain Leakage Current Degradation in Thin-Oxide n-MOSFET's, International Conference on Solid State Devices and Materials (SSDM), Hiroshima, Japan
1998 T. Wang, Hot Carrier Effects on Flash EEPROM Reliability, Workshop on Deuterium Processing and Hot Electron Reliability
1997 T. Wang, L. P. Chiang, N. K. Zous, T. E. Chang and C. Huang, Characterization of Various Stress-Induced Oxide Traps in MOSFET's by Using a Novel Transient Current Technique, IEEE International Electron Device Meeting(IEDM), Washington, U.S.A.
1997 T. E. Chang, L. P. Chiang, C. W. Liu, N. K. Zous and T. Wang., Temperature Effect on Off-State Drain Leakage Current in a Hot-Carrier Stressed n-MOSFET, International Conference on Solid State Devices and Materials (SSDM), Hamamatsu, Japan
1997 T. Wang, L. P. Chiang, T. E. Chang, N. K. Zous, K. Y. Shen and C. Huang., A New Technique to Measure an Oxide Trap Density in a Hot Carrier Stressed n-MOSFET, Int. Reliability Phys. Symp. (IRPS), Denver.U.S.A.
1997 T. Wang, T. E. Chang, L. P. Chiang, N. K. Zous and C. Huang, Investigation of Oxide Charge Trapping and Detrapping in a n-MOSFET, Int. Reliability Phys. Symp. (IRPS), Denver, U.S.A.
1996 T. E. Chang, T. Wang, S. C. Lin and C. H. Wang, Simulation of Hot Electron Effects in n-MOSFET's at Low Drain Voltages, IEEE International Electron Device Meeting(IEDM), Hsin-Chu, Taiwan
1996 T. Wang, T. E. Chang, L. P. Chiang and C. Huang., Simulation and Characterization of Oxide Charge Injection in MOSFET Structures, International Electronic Devices and Materials Symposiums (EDMS), Hsin-Chu, Taiwan
1996 T. Wang, Oxide Reliability simulation and Characterization in MOSFET Structures, Semiconductor Technology CAD workshop and Exhibition, Hsin-Chu, Taiwan
1996 T. Wang, A New Oxide Trap Characterization Technique for a Hot Carrier stressed MOSFET, 1st Photonics and Semiconductor Device Reliability Workshop, Hsin-Chu, Taiwan
1996 T. Wang, T.E. Chang, L. P. Chiang, C. Huang and J. C. Guo, Mechanisms and Characteristics of Oxide Charge Detrapping in n-MOSFET's, International Symp. on VLSI Tech. (VLSI), Hawaii, U.S.A
1996 T. Wang, T.E. Chang, L. P. Chiang and C. Huang, Field Enhanced Oxide Charge Detrapping in n-MOSFET's, International Reliability Physics Symposium (IRPS), Dallas, U.S.A.
1995 C. Huang, T. Wang, N. C. Peng, A. Chang, T. Chen, S. Wu and F. C. Shone, Related Reliability Issues of Band-to-Band Tunneling Induced Hot Hole Injection in Flash EEPROM's, IEEE Non-Volatile Semiconductor Memory Workshop (NVSM), Calif. U.S.A.
1995 T. E. Chang, T. Wang, and C. Huang, Interface Trap Induced Drain Leakage Current in Various n-MOSFET Structures, International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan
1995 C. Huang, T. Wang, T. Chen, N. C. Peng, A. Chang, F. C. Shone, Characterization and Simulation of Hot-Carrier Effect on Erasing Gate Current in Flash EEPROM's, International Reliability Physics Symposium (IRPS), Las Vegas, U.S.A.
1994 T. Wang, T. E. Chang and C. Huang, A Comparative Study of Interface Trap Induced Drain Leakage in Various n-MOSFET Structures,, International Conference on Solid State Devices and Materials (SSDM), Osaka, Japan
1994 T. Wang, T. E. Chang and C. Huang, Interface Trap Induced Thermionic and Field Emission Current in OFF-State MOSFET’s, IEEE International Electron Devices Meeting (IEDM), San Francisco, U.S.A.
1994 T. Wang, C. Huang and T. E. Chang, T. Wang, C. Huang and T. E. Chang, International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan
1994 T. Wang, C. Huang, T. E. Chang, J. W. Chou and C. Y. Chang, Lateral Field Enhanced Band-Trap-Band Tunneling Current in a 0.5m “OFF” State MOSFET’s., International Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan,
1994 T. Wang, C. Huang, P. C. Chou, S. S. Chung and T. E. Chang, Analysis of Interface Trap Induced Performance Variation in LDD MOSFET’s, International Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan
1994 T. Wang, C. Huang, T. E. Chang, J. W. Chou and C. Y. chang, Lateral Field Enhanced Band-Trap-Band Tunneling Current in a 0.5m “OFF” State MOSFET’s, 52nd Device Research Conference (DRC), Colorado, U.S.A.
1994 T. Wang, C. Huang, P. C. Chou and S. Chung, Simulation of Interface State Generation Effects in LDD MOSFETs, 5th International Conference on Numerical Modeling of Process and Devices for Integrated Circuits (NUPAD), Hawwaii, U.S.A.
1994 T. H Hsieh, H. Wang, T. Wang, T. H. Chen, Y. C. Chiang, S. T. Tseng, A. Chen and Y. E. Chang, An Ultra Low Cost and Miniature 950-2050 MHz GaAs MMIC Downconverter,”, IEEE AP-S International Symposium and URSI Radio Science Meeting, Seattle, Washington, U.S.A.
1993 Chimoon Huang; Tahui Wang, Transient simulation of EPROM writing characteristics with a novel hot electron injection model, International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan
1992 T. Wang, T. H. Hsieh, and T. W. chen, Quantum Well Geometrical Effects on Two-dimentional electron Mobility in AlGaAs/GaAs hetero-Structures, International Conference on Solid state Devices and Materials (’92 SSDM), Tsukuba, Japan
1991 Tahui Wang; Sheng-Jyh Wu, Mixed mode simulation of slow transient effects in AlGaAs/GaAs HEMT inverters, IEEE Custom Integrated Circuits Conference
1991 Tahui Wang; Sheng-Jyh Wu, Integrated device and circuit simulation of deep donor trapping effects in DCFL and SCFL inverters, IEEE Int. Symposium on Circuits and Systems
1990 T. Wang and J. S. Pan, Quasi-Ballistic Transport Effect on AC Performance of GaAs MESFETs, Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan,
1990 T. Wang and S.J. Wu, Mixed Mode Simulation of Deep Traps Induced slow Transient Effects on HEMT Inverters, Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan,
1990 Tahui Wang; Cherig-Hsiang Hsieh, Numerical Simulation Of Two-dimensional Electron Transport In AlGaAs/InGaAs/GaAs Pseudomorphic Hemt's, Numerical Modeling of Processes and Devices for Integrated Circuits (NUPAD)
1989 C. Yu and T. Wang, Anomalous Transient Phenomena in the AlGaAs/GaAs HEMT’s due to the DX Traps, Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan
1989 C.H. Hsieh and T. Wang, Modeling of Hot Electron Properties in Quantum Well Devices, Electronic Devices and Materials Symposium (EDMS), Hsin-Chu, Taiwan
1984 V. Robbins, K. Brennan, T. Wang, K. Hess and G. Stillman., Impact Ionization Coefficients in <100> and <111> Silicon, 42nd Device Research Conference, Santa Babara, U.S.A.
1984 T. Wang, K. Brennan and K. Hess, Bremstrahlung from Hot Electrons in Si MOSFET’s, 17th Physical Electronics Workshop, U.S.A.
1982 T. Wang and H. Morkoc, A Novel Camel Diode Gate GaAs FET, 15th Physical Electronics Workshop, U.S.A.
年度 計畫名稱 參與人 職稱/擔任之工作 計畫期間 補助/委託或合作機構
2016 電荷擷取式3D NAND快閃記憶體可靠性量測及氮化矽內儲存電荷傳輸模擬 汪大暉 主持人 2016.08.23 ~ 2019.07.23 科技部
2015 一種七奈米以下具有單分子層量子侷限效應之二維電子通道材料的三維場效電晶體元件研究 汪大暉 共同主持人 2015.08.23 ~ 2018.07.23 科技部
2015 電阻式記憶體陣列內新式可靠性效應與物理機制、統計分析量測及三度空間可靠性模擬 汪大暉 主持人 2015.08.23 ~ 2018.07.23 科技部
2014 次10 奈米以下具有先進通道材料之非平面場效電晶體元件開發 汪大暉 共同主持人 2014.08.23 ~ 2015.07.23 科技部
2014 次10奈米電阻式隨機存取記憶體開發(3/3) (奈米國家型計劃) 汪大暉 共同主持人 2014.07.23 ~ 2015.06.23 科技部
2013 一種利用隨機電報雜訊量測方法對金屬矽化物能障降低製程所導致的接面缺陷之定量化探討 汪大暉 共同主持人 2013.08.23 ~ 2014.07.23 科技部
2013 單電荷與輻射效應在先進CMOS和SONOS 元件可靠性之統計量測與模式 汪大暉 主持人 2013.08.23 ~ 2016.07.23 科技部
2013 電阻式記憶元件操作特性與可靠性之統計測量及三度空間原子與電荷傳輸模擬  汪大暉 主持人 2013.08.23 ~ 2015.07.23 科技部
2013 一種利用隨機電報雜訊量測方法對金屬矽化物能障降低製程所導致的接面缺陷之定量化探討 汪大暉 共同主持人 2013.08.23 ~ 2014.07.23 科技部
2013 次10奈米電阻式隨機存取記憶體開發(2/3) (奈米國家型計劃) 汪大暉 共同主持人 2013.07.23 ~ 2014.06.23 科技部
2012 一種可應用於生物檢測之混合感測器/記憶體技術的奈米鰭式場效電晶體 汪大暉 共同主持人 2012.08.23 ~ 2013.07.23 科技部
2012 RTN and NBTI induced ΔVt distribution and qualification 汪大暉 2012.08.23 ~ 2017.07.23 聯華電子
2012 次10奈米電阻式隨機存取記憶體開發(1/3) (奈米國家型計劃) 汪大暉 共同主持人 2012.06.23 ~ 2015.05.23 科技部
2010 奈米SONOS元件內單電子效應,可靠性物理及創新研究 汪大暉 主持人 2010.08.23 ~ 2013.07.23 科技部
2010 量子線矽、鍺、砷化鎵奈米CMOS元件內電荷傳輸模擬與可靠性 汪大暉 主持人 2010.08.23 ~ 2013.07.23 科技部
2010 Random Telegraph Noise Physics, Characterization and 3D Atomistic Simulation in High-K Gate Dielectric CMOS 汪大暉 2010.08.23 ~ 2011.07.23 台灣積體電路製造股份有限公司
2008 矽鍺量子井通道元件中電洞傳輸之蒙地卡羅模擬 汪大暉 2008.03.23 ~ 2009.03.23 台灣積體電路製造股份有限公司
2007 耐高壓元件的可靠度模型及特性分析 汪大暉 2007.10.23 ~ 2008.09.23 立錡科技
2007 次32奈米CMOS元件可靠性分析,量子結構效應,與蒙地卡羅電荷傳輸模擬 汪大暉 主持人 2007.08.23 ~ 2010.07.23 科技部
2007 高介電係數CMOS元件內載子移動率之退化機制 汪大暉 2007.01.23 ~ 2007.12.23 台灣積體電路製造股份有限公司
2006 具有物理意義的LDMOS電路模型-包括雜訊與自我加熱效應 汪大暉 2006.09.23 ~ 2007.08.23 台灣積體電路製造股份有限公司
2006 次50奈米二位元儲存氮化矽快閃式記憶體元件之結構、電荷傳輸與可靠性研究 汪大暉 主持人 2006.08.23 ~ 2009.07.23 科技部
2006 含金屬閘極與先進介電層奈米CMOS元件之物理與可靠性研究 汪大暉 2006.01.23 ~ 2006.12.23 台灣積體電路製造股份有限公司
2005 A Direct Extraction Apprach to SPICE Modeling and Self-Heating Effects in High-voltage 40V LDMOS Device 汪大暉 2005.07.23 ~ 2006.06.23 台灣積體電路製造股份有限公司
2005 鰭式金氧半場效電晶體 汪大暉 2005.02.23 ~ 2006.01.23 台灣積體電路製造股份有限公司
2005 Study of High -k Gate Dielectric Reliability and Trap Properties 汪大暉 2005.01.23 ~ 2005.12.23 台灣積體電路製造股份有限公司
2004 奈米CMOS元件量子效應與電荷傳輸模擬及電性與可靠性分析 汪大暉 主持人 2004.08.23 ~ 2007.07.23 科技部
2004 high voltage LDMOS device model and characterization 汪大暉 2004.01.23 ~ 2004.12.23 台灣積體電路製造股份有限公司
2004 超薄氧化層RF CMOS元件與SiGe HBT元件低頻雜訊之模式建立與特性分析 汪大暉 2004.01.23 ~ 2004.12.23 台灣積體電路製造股份有限公司
2003 雙位元儲存氮化矽快閃式記憶元件技術及可靠性 汪大暉 主持人 2003.08.23 ~ 2006.07.23 科技部
2003 射頻CMOS元件雜訊與可靠性研究 汪大暉 2003.01.23 ~ 2003.12.23 台灣積體電路製造股份有限公司
2002 射頻CMOS元件模式與Flicker Noise分析 汪大暉 2002.08.23 ~ 2003.07.23 矽統科技股份有限公司
專利名稱 專利編號 專利國別 作者
Method of Programming Cell in Memory and Memory Apparatus Utilizing the Method 7916551 US W.J. Tsai, C.W. Lee and Tahui Wang
Method and Apparatus For Electroluminescence 7439085 US C.C. Yeh, S.H. Ku, Tahui Wang, C.Y. Lu
The Method of Combining Multilevel Cells For an Error Correction Scheme 7243277B2 US H.C. Chang, Tahui Wang, J.T. Wu
電致發光的方法與裝置 268000 中華民國 葉致鍇、古紹泓、汪大暉、盧志遠
用於電晶體暫態與直流電性分析之量測電路及其方法 256479 中華民國 汪大暉、詹前泰
組合多準位記憶單元並使其具備錯誤更正機制的方法 243376 中華民國 張錫嘉、吳介琮、汪大暉
Circuit to Simulate the Polarization Relaxation Phenomenon of the Ferroelectric Memory 6552921B2 US C.W. Tsai, Tahui Wang, S.Y. Lee
Method of Programming and Erasing a SNNNS Type Non-Volatile Memory Cell 6512696 US T.H. Fan, T.C. Lu, Samuel C.S. Pan, Tahui Wang
Accelerated testing method and circuit for non-volatile memory 6445614 US W.J. Tsai, N.K. Zous, Tahui Wang
Qualification Test Method and Circuit for a Non-Volatile Memory 6563752B2 US W.J. Tsai, N.K. Zous, Tahui Wang
Reliability Test Method and Circuit for Non-Volatile Memory 6512710B1 US W.J. Tsai, L.T. Huang, N.K. Zous, Tahui Wang
快閃式記憶體中一種適合低汲極電壓操作之熱電子程式化的方法 133437 中華民國 汪大暉
模擬鐵電記憶體極化鬆釋現象之電路結構 174367 中華民國 蔡慶威、汪大暉、李學儀
非揮發性記憶體之可靠性驗證方法與電路 172129 中華民國 蔡文哲、鄒年凱、汪大暉
非揮發性記憶體之加速測試方法與電路 172128 中華民國 蔡文哲、鄒年凱、汪大暉
SNNNS類非揮發性記憶胞之寫入與清除方法 167367 中華民國 范左鴻、盧道政、潘正聖、汪大暉
非揮發性記憶體之可靠性測試方法與電路 173067 中華民國 蔡文哲、黃蘭婷、鄒年凱、汪大暉
具多重閘極絕緣層之非揮發性記憶體元件 167366 中華民國 范左鴻、盧道政、潘正聖、汪大暉
國家 學校名稱 系所 學位
台灣 國立台灣大學 電機工程
美國 伊利諾大學香檳校區 電機工程 博士
服務機關名稱 單位 職務
國立交通大學 國際半導體產業學院 合聘教授
Journal of Computational Electronics, Springer 副編輯
Electron Device Letters, IEEE 編輯
美國惠普公司 研究工程師
國立交通大學 電子工程系 教授
年度 獎項名稱 頒獎單位
2010 傑出研究獎 國立交通大學
2009 傑出研究獎 國立交通大學
2008 傑出研究獎 國立交通大學
2007 傑出研究獎 國立交通大學
2005 最佳學生論文獎 VLSI Symp. on Technology
2005 TSMC Student Research Award (as thesis advisor) 台灣積體電路製造股份有限公司
2004 最佳論文獎 IEEE Int. Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA)
1991 傑出教學獎 教育部
1990 青年研究論文獎 中國工程師學會