Orbit

簡  昭欣
合聘師資
姓名 簡 昭欣
職稱 教授
電子郵件 chchien@faculty.nctu.edu.tw
聯絡電話 03-5712121 ext. 54252
研究專長
一、先進奈米元件閘極工程之研究
二、有機薄膜元件及記憶體之研究
三、奈米微晶粒記憶體及其量子現象之探討
四、矽鍺與III-V化合物高遷移率元件
簡介

簡昭欣,1968年5月24日生。台灣南投縣人,交通大學電子工程系學士,交通大學電子工程系博士。1999年9月,至國家奈米元件實驗室擔任副研究員。2005年8月至交通大學服務,現任國立交通大學電子系所教授。
年度 論文名稱
2016 Yi-He Tsai, Chen-Han Chou, An-Shih Shih, Yu-Hau Jau, Wen-Kuan Yeh, Yu-Hsien Lin, Fu-Hsiang Ko, and Chao-Hsin Chien, Improving Thermal Stability and Interface State Density of High-κ Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium, IEEE Trans. Elec. Dev. Vol. 37, No.11, p.1379-1382, Nov 2016
2016 Ming-Li Tsai, Jun-Yu Ko, Shin-Yuan Wang, and Chao-Hsin Chien, Interface Characterization of HfO2/GaSb MOS Capacitors with Ultrathin Equivalent Oxide Thickness by Using Hydrogen Plasma Treatment, IEEE Trans. Elec. Dev. Vol. 63, No.9, p.3459-3460, Sep 2016
2016 Chung-Chun Hsu, Wei-Chun Chi, Yi-He Tsai, Chen-Han Chou, Che-Wei Chen, Hung-Pin Chien, Shang-Shiun Chuang, Guang-Li Luo, Yao-Jen Lee, and Chao-Hsin Chien, Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs, IEEE Trans. Elec. Dev. Vol. 63, No.7, p.2714-2721, Jun 2016
2016 Chen-Han Chou, Hao-Hsuan Chang, Chung-Chun Hsu, Wen-Kuan Yeh and Chao-Hsin Chien, Low-leakage Tetragonal ZrO2 (EOT < 1 nm) with In Situ Plasma Interfacial Passivation on Germanium, Elec. Dev. Lett. VOL. 37, NO. 2, p.138-141, 2016
2016 Chung-Chun Hsu, Yi-He Tsai, Che-Wei Chen, Jyun-Han Li, Yu-Hsien Lin, Yao-Jen Lee, Guang-Li Luo, and Chao-Hsin Chien, High-Performance Schottky Contact Quantum-Well Germanium Channel pMOSFET With Low Thermal Budget Process, Elec. Dev. Lett. VOL. 37, NO. 1, p.8-11, 2016
2015 Chung-Chun Hsu, Chen-Han Chou, Shin-Yuan Wang, Wei-Chun Chi, Guang-Li Luo and Chao-Hsin Chien, Fabricating a n+-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal, Appl. Phys. Lett., 107, 113503 (2015)
2014 Che-Wei Chen, Ju-Yuan Tzeng, Cheng-Ting Chung, Hung-Pin Chien, Yang Zhou, Chao-Hsin Chien and Guang-Li Luo, High Performance Germanium P and N MOSFETs with NiGe Source/Drain, IEEE Trans. Elec. Dev., Vol. 61 , No. 8, p.2656 (2014)
2014 Hung-Chi Wu and Chao-Hsin Chien, Highly Transparent, High Performance IGZO-TFTs Fabricated Using the Selective Formation of IGZO Source and Drain Electrodes, Elec. Dev. Lett. VOL. 35, NO. 6, p.645, 2014
2014 Tsung Yu Han, Chao-Hsin Chien, Guang-Li Luo, Chao-Ching Cheng, Chih-Hsin Ko, Clement H. Wann, Chi-Chung Kei and Chien-Nan Hsiao, Experimental demonstration of (111)-oriented GaAs metal oxide semiconductor field-effect-transistors with hetero-epitaxial Ge Source Drain, ECS Journal of Solid State Science and Technology, 3 (4) P86-P90 (2014)
2014 Hung-Chi Wu, Tung-Sheng Li and Chao-Hsin Chien, Effect of Mg doping on the electrical characteristics of high performance IGZO thin film transistors, ECS Journal of Solid State Science and Technology, 3 (2) Q1-Q4 (2014)
2014 Che-Wei Chen, Ju-Yuan Tzeng, Cheng-Ting Chung, Hung-Pin Chien, Chao-Hsin Chien, Guang-Li Luo, Pei-Yu Wang, and Bing-Yue Tsui , Enhancing the Performance of Germanium Channel NMOSFET Using Phosphorus Dopant Segregation, Elec. Dev. Lett. VOL. 35, NO. 1, p. 6, JANUARY 2014
2014 Che-Wei Chen, Cheng-Ting Chung, Ju-Yuan Tzeng, Pang-Sheng Chang, Guang-Li Luo, and Chao-Hsin Chien, Body-tied Germanium Tri-Gate Junctionless PMOSFET with Insitu Boron Doped Channel, Elec. Dev. Lett. VOL. 35, NO. 1, p.12, JANUARY 2014
2013 Cheng-Ting Chung, Che-Wei Chen, Jyun-Chih Lin, Che-Chen Wu, Chao-Hsin Chien, Guang-Li Luo, Chi-Chung Kei and Chien-Nan Hsiao, Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ION/IOFF Ratio Ge FinFETs, IEEE Trans. Elec. Dev. Vol. 60, No. 6, p.1878, 2013
2013 Che-Wei Chen, Cheng-Ting Chung, Ju-Yuan Tzeng, Pin-Hui Li, Pang-Sheng Chang, Chao-Hsin Chien and Guang-Li Luo, Germanium N and P Multi-fin Field Effect Transistors with High Performance Germanium (Ge) p+/n and n+/p Heterojunctions Formed on Si Substrate, IEEE Trans. Elec. Dev., Vol. 60 , No. 4, p.1334 (2013)
2013 Hung-Chi Wu and Chao-Hsin Chien, High performance InGaZnO thin film transistor with InGaZnO source and drain electrodes, Appl. Phys. Lett., 102, 062103 (2013)
2013 Hung-Chi Wu and Chao-Hsin Chien, Improving electrical properties of bottom-gate poly (3-hexylthiophene) thin film transistor using CF4 plasma treatment, Elec. Dev. Lett., Vol. 34, No. 4, p.538 (2013)
2013 Che-Wei Chen, Cheng-Ting Chung, Jyun-Chih Lin, Guang-Li Luo and Chao-Hsin Chien, High on/off ratio and greatly low leakage p+/n and n+/p germanium/silicon heterojunction diodes, Appl. Phys. Express 6(2013) 024001
2013 Yu-Yen Kuo and Chao-Hsin Chien, Sinter-free transferring of anodized TiO2 nanotube-array onto a flexible and transparent sheet for dye-sensitized solar cells, Electrochimica Acta, Vol. 91, pp.337-343, Feb. 2013
2013 Yu-Hsien Lin, and Chao-Hsin Chien, HfO2 Nanocrystal Memory on SiGe Channel, Solid-State Electronics, Vol.80, February, pp.5-9, 2013
2012 Chia-Hao Chang and Chao-Hsin Chien, Enhanced Performances of Poly(3-hexylthiophenes) Based Thin Film Transistors Using Double-coated Active Layer, ECS J. Solid State Sci. Technol. 2012, Volume 1, Issue 6, Pages Q130-Q134
2012 Che-Wei Chen, Cheng-Ting Chung, Guang-Li Luo and Chao-Hsin Chien, Body-Tied Germanium Fin Field Effect Transistors(FinFETs) Directly on Si Substrate, IEEE Elec. Dev. Lett. Vol. 33, No.12, pp.1678-1680, 2012
2012 Chia-Hao Chang and Chao-Hsin Chien, A study of bulk current mechanism in P3HT-based thin film transistors and approach for current suppression, Organic Electronics Volume 13, Issue 11, November 2012, Pages 2620–2626
2012 Yu Yen Kuo, Tze Huei Li, Chiung-Yuan Lin, Jing-Neng Yao and Chao Hsin Chien, Hydrothermal crystallization and modification of surface hydroxyl groups of anodized TiO2 nanotube-arrays for more efficient photoenergy conversion, Electrochimica Acta 78 (2012) 236– 243
2012 Min-Cheng Chen , Hao-Yu Chen , Chia-Yi Lin, Chao-Hsin Chien, Tsung-Fan Hsieh,Jim-Tong Horng , Jian-Tai Qiu, Chien-Chao Huang, Chia-Hua Ho and Fu-Liang Yang, A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications, Sensors 2012, 12, 3952-3963; doi:10.3390/s120403952
2012 Yu-Hsien Lin, Hsin-Chiang You, and Chao-Hsin Chien, Two-bit/four-level Pr2O3 trapping layer for silicon-oxide-nitride-oxide-silicon-type flash memory, J. Vac. Sci. Technol. B 30, 011201 (2012)
2012 Yu-Hsien Lin, and Chao-Hsin Chien, Nanoscale 2-bit/cell HfO2 Nanocrystal Flash Memory, IEEE Trans on Nanotechnology, Vol. 11, No. 2, p. 412, March ( 2012)
2012 Yu-Yen Kuo, Jui-Guo Lin and Chao-Hsin Chien, Enhancing  charge collection in dye-sensitized solar cells by trimming  sidewall  of  the TiO2 nanotubes, Journal of The Electrochemical Society, 159 (2) K46-K49 (2012)
2011 Chia-Hao Chang and Chao-Hsin Chien, Functionalized single-walled carbon nanotubes blended P3HT based thin film transistors with multi-walled carbon nanotube source and drain electrodes, Elec. Dev. Lett. Vol.32, No.10, p.1457, 2011
2011 Chia-Hao Chang, Meng-Fei Chen, Chao-Hsin Chien, An investigation of transient effects in poly(3-hexylthiophenes) based thin film transistors caused by oxygen and water molecules, J. Electrochem. Soc. 158 (9) H854-H859 (2011)
2011 Hou-Yu Chen, Chun-Chi Chen, Fu-Kuo Hsueh, Jan-Tsai Lin, Chih-Yen Shen, Chiung-Chih Hsu, Shyi-Long Shy, Bih-Tiao Lin, Cheng-San Wu, Chao-Hsin Chien, Chenming Hu, Chien-Chao Huang and Fu-Liung Yang, A Novel Nano-Injection Lithography Application for 16-nm Node Device Fabrication, Trans. on Electron Devices VOL. 58, NO. 11, NOVEMBER 2011
2011 Hou-Yu Chen, Chia-Yi Lin, Min-Cheng Chen, Chien-Chao Huang, and Chao-Hsin Chien, NiSi Formation using Pulsed Laser Annealing for nMOSFET Performance Improvement, J. Electrochem. Soc. 158 (8) H840-H845 (2011)
2011 Yi-Hsien Lu, Chao-Hsin Chien, Po-Yi Kuo,a Ming-Jui Yang, Hsiao-Yi Lin and Tien-Sheng Chao, High-Performance Poly-Si TFTs of Top-Gate with High-Metal-Gate Combine the Laser Annealed Channel and Glass Substrate, Electrochem. Soc. Lett. 14 (1) H17-H20 (2011)
2011 Hou-Yu Chen , Chia-Yi Lin , Min-Cheng Chen , Chien-Chao Huang , and Chao-Hsin Chien, Fabrication of High- Sensitivitye Poly-Si Nanowire FET pH Sensor using Conventional CMOS Technology, Jpn. Journal of Applied Physics, Volume 50, Issue 4, pp. 04DL05-04DL05-5 (2011)
年度 論文名稱
2016 Yu-Che Chou, Chung-Chun Hsu, Cheng-Ting Chun, Chen-Han Chou, Ming-Li Tsai, Yi-He Tsai,Wei-Li Lee, Shin-Yuan Wang, Guang-Li Luo, and Chao-Hsin Chien, Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation, IEEE NANO, Poster Session 1, Poster 1-23, August 2016
2016 Chung-Chun Hsu, Wei-Chun Chi, Guang-Li Luo, Yao-Jen Lee, and Chao-Hsin Chien, Experimental Realization of Dopant Segregation Ge NMOSFET Using Microwave-Activated Annealing, European Materials Research Society, Program K, K.PI.23, May 2016
2016 Chen-Han Chou, Chung-Chun Hsu, Wen-Kuan Yeh, Steve S. Chung and Chao-Hsin Chien, 3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor, Silicon Nanoelectronics Workshop, Session 2, Poster 2-18, June 2016
2016 Yu-Hau Jau, Chen-Han Chou, Yi-He Tsai, Yu-Hsien Lin and Chao-Hsin Chien, Enhancing Thermal Stability of Nickel-Germanide Alloy up to 600 C by Using Metal Passivation, The Electrochemical Society meeting, June (2016)
2015 Chen-Han Chou, Chung-Chun Hsu, Steve S. Chung and Chao-Hsin Chien, 3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor, Silicon Nanoelectronics Workshop, T5-19 June 2015
2015 Wei-Chun Chi, Chung-Chun Hsu, Chen-Han Chou, An-Shih Shih, Yao-Jen Lee and Chao-Hsin Chien, Fabrication of Low-Temperature (< 400 C) Germanium MOSCaps by Microwave Thermal Oxidation, SSDM conference, PS-1-6,Sep. 2015
2015 Shin-Yuan Wang, Chao-Hsin Chien*, Jin-Ju Lin, Chun-Yen Chang, InGaAs Metal-Oxide-Semiconductor FETs with Self-Aligned Ni-Alloy Source/Drain, IEEE IPFA, June ,P415-418 (2015)
2014 Hung-Chi Wu and Chao-Hsin Chien, Nearly fully transparent InGaZnO thin film transistors with Mo-InGaZnO electrode, IEEE 2014 Intl. Conf. on Information Science, Electronics and Electrical Engineering (ISEEE), April 26-28 Sapporo City, Hokkaido, Japan
2014 Che-Wei Chen, Jyun-Han Li, Hung-Pin Chien, Ju-Yuan Tzeng, Cheng-Ting Chung, Guang-Li Luo, Yu-Hsien Lin, and Chao-Hsin Chien, Investigation of NiSiGe Schottky Junction for Germanium P-channel Quantum Well Logic Device Applications, Proc. MRS Spring Meeting, San Francisco, April 21-25, 2014
2014 Chao-Hsin Chien, Ge Channel MOSFETs Directly on Silicon, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), invited talk
2014 Chao-Hsin Chien, Body-tied Ge Tri-Gate Junctionless MOSFETs Directly on Si with NiGe Source/Drain, IEEE China Semiconductor Technology International Conference 2014, invited talk
2013 Chao-Hsin Chien, Ge/Si Heterojunction Diodes and Ge Channel FinFETs Directly on Si, IEEE Nanotechnology materials and devices conference 2013, Tainan, Taiwan, invited talk
2013 Cheng-Ting Chung, Guang-Li Luo, Che-Wei Chen, and Chao-Hsin Chien, An Alternative Technique for GeOI Fabrication, Int. Conf. on Solid State Devices and Materials (SSDM), 2013
2013 Che-Wei Chen, Cheng-Ting Chung, Ju-Yuan Tzeng, Guang-Li Luo, and Chao-Hsin Chien, Ge N-channel Omega-Gate Field Effect Transistors with [010] Channel Direction, Int. Conf. on Solid State Devices and Materials (SSDM), 2013
2013 Chao-Hsin Chien, High Performance Ge/Si Heterojunctions and Ge MOSFETs Directly on Si Substrate, IEEE China Semiconductor Technology International Conference 2013, invited talk
2012 Cheng-Ting Chung, Che-Wei Chen, Guang-Li Luo, Jyun-Chih Lin, Chao-Hsin Chien, First Experimental Ge CMOS FinFETs Directly on SOI substrate, Intl. Elec. Dev. Meeting (IEDM), San Francisco, 2012, pp. 383-386
發表日期 專利名稱 專利編號 專利國別 作者
2016/09/30 Semiconductor Devices and Methods of Manufacture Thereof Samuel C. Pan , Chao-Hsin Chien, and Chen-Han Chou
以(110)單軸拉伸應變提升電子遷移率之N型鍺場效電晶體 中華民國 羅廣禮、簡昭欣
Architecture of a n-type metal-oxide-semiconductor transistor with a compressive strained silicon-germanium channel fabricated on a silicon (110) substrate U.S.A. Guangli Luo, Chao-Hsin Chien, Tsung-Hsi Yang, Chun-Yen Chang
2015/10/30 Semiconductor Device and Formation Thereof U.S.A. Chao-Hsin Chien, Cheng-Ting Chung, Che-Wei Chen
2007/09/30 在矽(110)基板上設有壓縮應變矽鍺通道之N型金氧半電晶體架構 中華民國 羅廣禮、簡昭欣
利用矽酸鉿奈米微粒製備之非揮發性快閃記憶體 中華民國 簡昭欣、林慶宗、林育賢、張俊彥、雷添福
呂正傑、簡昭欣、楊明瑞、林宏道、胡塵滌、黃調元 中華民國 呂正傑、簡昭欣、楊明瑞、林宏道、胡塵滌、黃調元
鐵電元件之結構 中華民國 呂正傑、簡昭欣、楊明瑞、楊閔智、胡塵滌、黃調元
國家 學校名稱 系所 學位
台灣 國立交通大學 電子工程 博士
服務機關名稱 單位 職務
國立交通大學 國際半導體產業學院 合聘教授
國立交通大學 電子工程學系所 教授
國立交通大學 電子工程學系所 副教授
國立交通大學 電子工程學系所 助理教授
國家奈米元件實驗室 副研究員