Orbit

吳 介琮
姓名 吳 介琮
電子郵件 jt.wu@g2.nctu.edu.tw
聯絡電話 +886-3-5731840
個人網址 http://www.alab.ee.nctu.edu.tw/wpjtwu/
簡介

Jieh-Tsorng Wu was born in Taipei, Taiwan.  He received the B.S. degree in electronics engineering from National Chiao-Tung University, Taiwan, in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1983 and 1988, respectively.

 

From 1980 to 1982 he served in the Chinese Army as a Radar Technical Officer.  From 1982 to 1988, at Stanford University, he focussed his research on high-speed analog-to-digital conversion in CMOS VLSI.  From 1988 to 1992 he was a Member of Technical Staff at Hewlett-Packard Microwave Semiconductor Division in San Jose, CA, and was responsible for several linear and digital giga-hertz IC designs.  Since 1992, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan, where he is now a Professor. His current research interests are high-performance mixed-signal integrated circuits.

 

Dr. Wu is a Fellow of the IEEE. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits (JSSC) and a technical program subcommittee member of the IEEE International Solid-State Circuits Conference (ISSCC). Dr. Wu is also a member of Phi Tau Phi.

年度 論文名稱
2014 S-H Wu and J-T Wu, Background Calibration of Integrator Leakage in Discrete-Time Delta-Sigma Modulators, Analog Integrated Circuits and Signal Processing, No. 3, Vol. 81, pp 645-655
2013 S-H Wu and J-T Wu, A 81-dB Dynamic Range 16-MHz Bandwidth DS Modulator Using Background Calibration, IEEE Journal of Solid-State Circuits, No. 9, Vol. 48, pp2170-2179
2013 B-N Fang and J-T Wu, A 10-Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation, EEE Journal of Solid-State Circuits, No. 3, Vol. 48, pp670-683
2012 Y Chai and J-T Wu, A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC, IEEE Journal of Solid-State Circuits, No. 12, Vol. 47, pp2905-2915
2012 J-T Wu, C-C Huang, and C-Y Wang, CMOS Ultra-High-Speed Time-Interleaved ADCs, Nyquist AD Converters, Sensor Interfaces, and Robustness (Advances in Analog Circuit Design, 2012), Chapter 5, pp73-96
2011 W-H Tseng, C-W Fan, and J-T Wu, A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz, IEEE Journal of Solid-State Circuits, No. 12, Vol. 46, pp2845-2856
2011 C-C Huang, C-Y Wang, and J-T Wu, A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques, IEEE Journal of Solid-State Circuits, No. 4, Vol. 46, pp848-858
2011 W-H Tseng, J-T Wu, and Y-C Chu, A CMOS 8-Bit 1.6-GS/s DAC with Digital Random Return-to-Zero, IEEE Transactions on Circuits and Systems II: Express Briefs, No.1, Vol.58, pp1-5
2010 Y-H Chung and J-T Wu, A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC, IEEE Journal of Solid-State Circuits, No. 11, Vol. 45, pp2217-2226
2009 C-W Fan and J-T Wu, Jitter Measurement and Compensation for Analog-to-Digital Converters, EEE Transactions on Instrumentation and Measurement, No. 11, Vol. 58, pp3874-3884
2009 C-Y Wang and J-T Wu, A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection, IEEE Transactions on Circuits and Systems - I: Regular Papers, No. 6, Vol. 56, pp1102-1114
2007 Z-M Lee, C-Y Wang, and J-T Wu, A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration, IEEE Journal of Solid-State Circuits, No. 10, Vol. 42, pp2149-2160
2007 J-L Fan, C-Y Wang, and J-T Wu, A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs, IEEE Transactions on Circuits and Systems - I: Regular Papers, No. 6, Vol. 54, pp1213-1223
2006 J-M Chou, Y-T Hsieh, and J-T Wu, Phase Averaging and Interpolation Using Resistor Strings or Resistor Rings for Multi-Phase Clock Generation, IEEE Transactions on Circuits and Systems - I: Regular Papers, No. 5, Vol. 53, pp 984-991
2006 C-Y Wang and J-T Wu, A Background Timing-Skew Calibration Technique for Time-Interleaved Analog-to-Digital Converters, IEEE Transactions on Circuits and Systems - II: Express Briefs, No. 4, Vol. 53, pp299-303
2005 C-C Huang and J-T Wu, A Background Comparator Calibration Technique for Flash Analog-to-Digital Converters, IEEE Transactions on Circuits and Systems - I: Regular Papers, No. 9, Vol. 52, pp1732-1740
2005 H-C Liu, Z-M Lee, and J-T Wu, A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter with Digital Background Calibration, IEEE Journal of Solid-State Circuits, No. 5, Vol. 40, pp1047-1056
2003 C-C Hsu and J-T Wu, A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier, IEICE Transactions on Electronics,, No. 10, Vol. E86-C, pp2122-2128
2003 C-C Hsu and J-T Wu, A Highly Linear 125-MHz CMOS Switched-Resistor Programmable-Gain Amplifier, IEEE Journal of Solid-State Circuits, No. 10, Vol. 38, pp1663-1670
1999 W-Z Chen and J-T Wu, A 2 V 1.8 GHz BJT Phase-Locked Loop, IEEE Journal of Solid-State Circuits, No. 6, Vol. 34, pp784-789
1998 Vol. 34, No. 6, pp. 784-789, June 1999, A 2 V 2 GHz BJT Variable-Frequency Oscillator, IEEE Journal of Solid-State Circuits, No. 9, Vol. 33, pp1406-1410
1998 J-T Wu and K-L Chang, MOS Charge Pumps for Low-Voltage Operation, IEEE Journal of Solid-State Circuits, No. 4, Vol. 33, pp592-597
1998 J-T Wu and B. Wooley, A 100-MHz Pipelined CMOS Comparator, IEEE Journal of Solid-State Circuits, No. 6, Vol. 23, pp 1379--1385
1992 R. Walker, C. Stout, J-T Wu, B. Lai, C-S Yen, T. Hornak, P. Petruno, A Two-Chip 1.5-GBd Serial Link Interface, EEE Journal of Solid-State Circuits, No. 6, Vol. 27, pp1805-1811
年度 論文名稱
2016 C-M Chang and J-T Wu, A Computationally-Efficient PWM Technique for Digital Class-D Amplifiers,, 2016 IEEE International Symposium on Circuits and Systems
2013 S-H Wu and J-T Wu, Background Calibration of Integrator Leakage in Discrete-Time Delta-Sigma Modulators, The 11th IEEE New Circuits and Systems Conference
2013 C-L Chang and J-T Wu, A 1-V 100-dB Dynamic Range 24.4-kHz Bandwidth Delta-Sigma Modulator, 2013 IEEE International Symposium on Circuits and Systems
2012 Y Chai and J-T Wu, A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC, 2012 IEEE International Solid-State Circuits Conference
2011 Y-H Chung and J-T Wu, A 16-mW 8-Bit 1-GS/s Subranging ADC in 55nm CMOS, 2011 Symposium on VLSI Circuits
2011 W-H Tseng, C-W Fan, and J-T Wu, A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz, 2011 IEEE International Solid-State Circuits Conference
2010 C-C Huang, C-Y Wang, and J-T Wu, A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration, 2010 Symposium on VLSI Circuits
2009 Y-H Chung and J-T Wu, A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC, 2009 IEEE Asian Solid-State Circuits Conference
2006 Z-M Lee, C-Y Wang, and J-T Wu, A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration, 2006 IEEE Custom Integrated Circuits Conference
2005 J-L Fan and J-T Wu, A Robust Background Calibration Technique for Switched-Capacitor Pipelined ADCs, A Robust Background Calibration Technique for Switched-Capacitor Pipelined ADCs
2004 C-C Huang and J-T Wu, A Statistical Background Calibration Technique for Flash Analog-to-Digital Converters, 2004 IEEE International Symposium on Circuits and Systems
2004 H-C Chang, C-C Lin, T-Y Hsia, J-T Wu, and T-H Wang, Multi-Level Memory Systems Using Error Control Codes, 2004 IEEE International Symposium on Circuits and Systems
2004 H-C Liu, Z-M Lee, and J-T Wu, A 15-Bit 20MS/s CMOS Pipelined ADC with Digital Background Calibration, 2004 IEEE International Solid-State Circuits Conference
2003 C-C Hsu and J-T Wu, A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier,, 2003 Symposium on VLSI Circuits
2003 H-C Liu, Z-M Lee, and J-T Wu, A Digital Background Calibration Technique for Pipelined Analog-to-Digital Converters, 2003 IEEE International Symposium on Circuits and Systems
2003 J-M Chou, Y-T Hsieh, and J-T Wu, A 125MHz 8b Digital-to-Phase Converter, 2003 IEEE International Solid-State Circuits Conference
2002 C-C Hsu and J-T Wu, A 125 MHz -86 dB IM3 Programmable-Gain Amplifier, 2002 Symposium on VLSI Circuits
1999 W-Z Chen and J-T Wu, A 2 V 150 MHz CMOS Digital Phase Modulator for Fast-Switching Frequency Synthesis, 999 Symposium on VLSI Circuits
1999 Hsi-Yuan Wang and Jieh-Tsorng Wu, A Novel Delta-Sigma Time-to-Digital Converter Using Delay Line, 1999 International Analog VLSI Workshop
1998 J-T Wu, M-J Chen, and C-C Hsu, A 2 V 900 MHz CMOS Phase-Locked Loop, 1998 Symposium on VLSI Circuits
1998 W-Z Chen and J-T Wu, A 2 V 1.6 GHz BJT Phase-Locked Loop, 1998 IEEE Custom Integrated Circuits Conference
1997 W-Z Chen and J-T Wu, A 2 V 2 GHz BJT Variable-Frequency Oscillator, 1997 Bipolar/BiCMOS Circuits and Technology Meeting
1997 J-T Wu and K-L Chang, Low Supply Voltage CMOS Charge Pumps, 1997 Symposium on VLSI Circuits
1997 J-T Wu, H-D Chang, and P-F Chen, A 2 V 100 MHz CMOS Vector Modulator, 1997 IEEE International Solid-State Circuits Conference
1996 J-T Wu, Y-H Chang, and K-L Chang, 1.2 V CMOS Switched-Capacitor Circuits, 1996 IEEE International Solid-State Circuits Conference
1992 J-T Wu and R. Walker, A Bipolar 1.5 Gb/s Monolithic Phase-Locked Loop for Clock and Data Extraction, 1992 Symposium on VLSI Circuits
1992 R. Walker, J-T Wu, C. Stout, B. Lai, C-S Yen, T. Hornak, P. Petruno, A 2-Chip 1.5 Gb/s Bus-Oriented Serial Link Interface,, 1992 IEEE International Solid-State Circuits Conference
1990 J-T Wu, A Bipolar 1-GHz Multi-Decade Monolithic Variable-Frequency Oscillator, 1990 IEEE International Solid-State Circuits Conference
1988 J-T Wu and B. Wooley, A 100-MHz Pipelined CMOS Comparator for Flash A/D Converson,, 1988 IEEE Custom Integrated Circuits Conference
年度 計畫名稱 參與人 職稱/擔任之工作 計畫期間 補助/委託或合作機構
2014 Ultra-Low-Power Analog Integrated Circuits for Hearing Aids (I, II, III) Jieh-Tsorng Wu 2014.08.30 ~ 2017.07.30 National Science Council
2014 Smart-Glass Hearing Aid (I, II, III) Jieh-Tsorng Wu 2014.08.30 ~ 2017.07.30 National Science Council
2013 High-Performance Analog-Digital Conversion Techniques (I, II, III) Jieh-Tsorng Wu 2013.08.30 ~ 2016.07.30 National Science Council
國家 學校名稱 系所 學位
美國 史丹佛大學 電機工程 碩士
美國 史丹佛大學 電機工程 博士
台灣 國立交通大學 電子工程 學士
服務機關名稱 單位 職務
國立交通大學 國際半導體產業學院 合聘教授
國立交通大學 電子工程學系 教授
美國惠普公司 微波半導體部門 研究工程師
獎項名稱 頒獎單位
Fellow IEEE