Orbit

江 蕙如
姓名 江 蕙如
電子郵件 huiru.jiang@gmail.com
聯絡電話 +886-35131211
簡介

Iris Hui-Ru Jiang received her B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1995 and 2002, respectively. She was with VIA technologies from 2002 to 2005. Since 2005, she has joined the Department of Electronics Engineering at National Chiao Tung University, where she is currently a Professor. She has been a visiting scholar of IBM Austin Research Laboratory from 2013 to 2014, and has served as technical consultants of ITRI and Maxeda Technology. Her research interests lie in the field of Electronic Design Automation with an emphasis on physical design for nanometer ICs, including interaction between logic synthesis and physical design, timing analysis and optimization, design for manufacturability, and EDA applications to emerging technologies. Dr. Jiang has published more than 80 technical papers and held 11 patents. In particular, in recent 5 years, she has published more than 20 papers at top-tier conferences1 (including ACM/IEEE Design Automation Conference (DAC), IEEE/ACM International Conference on Computer-Aided Design (ICCAD), and ACM International Symposium on Physical Design (ISPD)) and more than 10 journal papers (including IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), and ACM Transactions on Design Automation of Electronic Systems (ACM TODAES)) in EDA field.

Dr. Jiang is a member of the Phi Tau Phi Scholastic Honor Society and the recipient of 2011 Chinese Institute of Electrical Engineering Outstanding Young Electrical Engineer Award. She received Best Paper Award Nomination from DAC 2016 and ISPD 2013 and Best in-track paper from ICCAD 2014. She and her students received the first place award at CAD Contest at ICCAD in 2012, two third place awards in 2013 and 2014 and the first place award in 2015 at TAU Timing Analysis Contest.

Dr. Jiang has served as an associate editor of premier EDA journal—IEEE TCAD—since 2016. She has served on technical program committees of EDA conferences at a variety of tracks, including logic synthesis, verification, physical design, and design for manufacturability tracks at DAC, ICCAD, ISPD, ASP-DAC, IWLS, and SLIP. She organized CAD contest at ICCAD2 from 2012 to 2014 (chair/co-chair), has organized CADathlon since 2016 (vice chair). She has served as the chair of DATC3 (Design Automation Technical Committee) of IEEE CEDA.
年度 論文名稱
2016 Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, and Iris Hui-Ru Jiang, Analytical clustering score with application to post-placement register clustering, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 21, no. 3, May. 2016, pp. 41:1—41:18
2015 Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, and Charles Chiang, Machine-learning-based hotspot detection using topological classification and critical feature extraction, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 3, Mar. 2015, pp. 460—470
2015 Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir Jamsek, and Gi-Joon Nam, Feature detection for image analytics via FPGA acceleration, IBM Journal of Research and Development, vol. 59, no. 2/3, Mar./May 2015, 8:0—8:10
2014 An-Che Cheng, Chia-Chih (Jack) Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, and Jing-Yang Jou, Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 20, no. 1, Nov. 2014, pp. 7:1—7:23
2014 Yu-Ming Yang, Iris Hui-Ru Jiang, and Sung-Ting Ho, PushPull: Short path padding for timing error resilient circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 4, Apr. 2014, pp. 558—570
2013 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, ECO optimization using metal-configurable gatearray spare cells, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 11, Nov. 2013, pp. 1722—1733
2013 Chih-Long Chang and Iris Hui-Ru Jiang, Pulsed-latch replacement using concurrent time borrowing and clock gating, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 2, Feb. 2013, pp. 242—246
2012 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, Timing ECO optimization via Bézier curve smoothing and fixability identification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 31, no. 12, Dec. 2012, pp. 1857—1866
2012 Iris Hui-Ru Jiang, Hua-Yu Chang, and Chih-Long Chang, WiT: Optimal wiring topology for electromigration avoidance, IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), vol. 20, no. 4, Apr. 2012, pp. 581—592
2012 Iris Hui-Ru Jiang and Hua-Yu Chang, ECOS: Stable matching based metal-only ECO synthesis, IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), vol. 20, no. 3, Mar. 2012, pp. 485—497
2012 Iris Hui-Ru Jiang, Chih-Long Chang, and Yu-Ming Yang, INTEGRA: Fast multibit flip-flop clustering for clock power saving, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 31, no. 2, Feb. 2012, pp. 192—204
2012 Jing-Wei Lin, Tsung-Yi Ho, and Iris Hui-Ru Jiang, Reliability-driven power/ground routing for analog ICs, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 17, no. 1, Jan. 2012, pp. 6:1—6:26
2012 Wan-Yu Lee, Iris Hui-Ru Jiang, and Tsung-Wan Mei, Generic integer linear programming formulation for 3D IC partitioning, Journal of Information Science and Engineering (JISE), vol. 28, no. 6, Nov. 2012, pp. 1129—1144
2009 Wan-Yu Lee and Iris Hui-Ru Jiang, Topology generation and floorplanning for low power applicationspecific network-on-chips, International Journal of Electrical Engineering (IJEE), vol. 16, no. 1, Feb. 2009, pp. 51—59
2006 Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, and Jing-Yang Jou, Reliable crosstalk-driven interconnect optimization, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 11, no. 1, Jan. 2006, pp. 88—103
2004 Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, and Kai-Yuan Chao, Simultaneous floorplan and bufferblock optimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 23, no. 5, May 2004, pp. 694—703
2000 Iris Hui-Ru Jiang, Yao-Wen Chang, and Jing-Yang Jou, Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 19, no. 9, Sep. 2000, pp. 999—1010
1999 Jiann-Horng Lin, Jing-Yang Jou, and Iris Hui-Ru Jiang, Internet-based hierarchical floorplan design, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Volume E82-A, no. 11, Nov. 1999, pp. 2414—2423
年度 論文名稱
2016 Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, OWARU: Free spaceaware timing-driven incremental placement, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2016), Austin, TX, USA, Nov. 2016, Austin, TX, USA
2016 Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, and Yih-Lang Li, OpenDesign flow database: The infrastructure for VLSI design and design automation research, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2016), Austin, TX, USA, Nov. 2016, Austin, TX, USA
2016 Hua-Yu Chang and Iris Hui-Ru Jiang, Multiple patterning layout decomposition considering complex coloring rules, Proc. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC-2016), Austin, TX, June 2016, Austin, TX
2016 An-Che Cheng, Iris Hui-Ru Jiang, and Jing-Yang Jou, Resource-aware functional ECO patch generation, Proc. 19th IEEE/ACM Design, Automation & Test in Europe (DATE-2016), Dresden, Germany, Mar. 2016, Dresden, Germany
2016 Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, and Bing Li, Reliability, adaptability and flexibility in timing: Buy a life Insurance for your circuits, Proc. ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2016), Macao, Jan. 2016, Macao
2016 Hua-Yu Chang and Iris Hui-Ru Jiang, DLX*: An exact and general multiple patterning layout decomposition framework, 27th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2016, Kaohsiung, Taiwan
2015 Chien-Pang Lu, Iris Hui-Ru Jiang and Chin-Hsiung Hsu, GasStation: Power and area efficient buffering for multiple power domain design, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2015), Austin, TX, USA, Nov. 2015, pp. 861—866, Austin, TX, USA
2015 Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, and Yu-Ming Yang, iTimerC 2.0: Fast incremental timing and CPPR analysis, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2015), Austin, TX, USA, Nov. 2015, pp. 890—894, Austin, TX, USA
2015 Yu-Ming Yang, King Ho Tam, and Iris Hui-Ru Jiang, Criticality-dependency-aware timing characterization and analysis, Proc. 52nd ACM/EDAC/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015, San Francisco, CA
2015 Chang Xu, Peixin Li, Guojie Luo, Yiyu Shi, and Iris Hui-Ru Jiang, Analytical clustering score with application to post-placement multi-bit flip-flop merging, Proc. ACM International Symposium on Physical Design (ISPD-2015), Monterey, CA, USA, Mar. 2015, pp. 93—100, Monterey, CA, USA
2015 Yu-Ming Yang, King Ho Tam, and Iris Hui-Ru Jiang, Timing characterization and analysis considering criticality dependency, 26th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2015, Hualien, Taiwan
2014 Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, and Jerry Hayes, Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2014), San Jose, CA, USA, Nov. 2014, pp. 382—388, San Jose, CA, USA
2014 Yu-Ming Yang, Yu-Wei Chang, and Iris Hui-Ru Jiang, iTimerC: Common path pessimism removal using effective reduction methods, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2014), San Jose, CA, USA, Nov. 2014, pp. 600—605, San Jose, CA, USA
2014 Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, and Charles Chiang, DRC-based hotspot detection considering edge tolerance and incomplete specification, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2014), San Jose, CA, USA, Nov. 2014, pp. 101—107, San Jose, CA, USA
2014 Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, and Jin-Fu Li, The overview of 2014 CAD contest at ICCAD, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2014), San Jose, CA, USA, Nov. 2014, p. 356, San Jose, CA, USA
2014 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, Functional ECO using metal-configurable gate-array spare cells, Proc. 51st ACM/EDAC/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014, pp. 1115—1120, San Francisco, CA
2014 Yen-Ting Yu, Yumin Zhang, Iris Hui-Ru Jiang, and Charles Chiang, Accurate and Efficient DRC-Based Range Pattern Matching with Incomplete Specification, 25th VLSI Design/CAD Symposium, Taichung, Taiwan, Aug. 2014, Taichung, Taiwan
2013 Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, and Natarajan Viswanathan, The overview of 2013 CAD contest at ICCAD, Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD-2013), San Jose, CA, Nov. 2013, p. 264, San Jose, CA
2013 Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, and Charles Chiang, Machine-learning-based hotspot detection using topological classification and critical feature extraction, Proc. 50th ACM/EDAC/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013, pp. 472—477, Austin, TX
2013 Chang-Cheng Tsai, Yiyu Shi, Guojie Luo, and Iris Hui-Ru Jiang, FF-Bond: Multi-bit flip-flop bonding at placement, Proc. 22nd ACM International Symposium on Physical Design (ISPD-2013), (Lake Tahoe) Stateline, NV, Mar. 2013, pp. 147—153, (Lake Tahoe) Stateline, NV
2013 Yu-Ming Yang, Iris Hui-Ru Jiang, and Sung-Ting Ho, PushPull: Short path padding for timing error resilient circuits, Proc. 22nd ACM International Symposium on Physical Design (ISPD-2013), (Lake Tahoe) Stateline, NV, Mar. 2013, pp. 50—57, (Lake Tahoe) Stateline, NV
2012 Iris Hui-Ru Jiang, Zhuo Li, and Yih-Lang Li, Opening: Introduction to CAD contest at ICCAD 2012, Proc. 30th IEEE/ACM International Conference on Computer Aided Design (ICCAD-2012), San Jose, CA, Nov. 2012, p. 341, San Jose, CA
2012 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, Timing ECO optimization using metal-configurable gate-array spare cells, Proc. 49th ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012, pp. 802—807, San Francisco, CA
2012 Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, and Charles Chiang, Accurate processhotspot detection using critical design rule extraction, Proc. 49th ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, June 2012, pp. 1163—1168, San Francisco, CA
2012 Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, and Aki S.-H. Chen, Novel pulsed-latch replacement based on time borrowing and spiral clustering, Proc. 21st ACM International Symposium on Physical Design (ISPD-2012), Napa, CA, Mar. 2012, pp. 121—128, Napa, CA
2012 Yen-Ting Yu, Iris Hui-Ru Jiang, Charles Chiang, Subarna Sinha, and Ya-Chung Chan, A novel DRC-based hotspot detection algorithm, 23rd VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2012, Kenting, Taiwan
2012 Wan-Yu Lee and Iris Hui-Ru Jiang, Online dynamic power management for multicore processors using reinforcement learning, ACM/IEEE Int'l Workshop on Timing Issues in the Specification & Synthesis of Digital Systems (TAU-2012), Taipei, Taiwan, Jan. 2012, Taipei, Taiwan
2011 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, Timing ECO optimization via Bézier curve smoothing and fixability identification, Proc. 30th IEEE/ACM International Conference on Computer Aided Design (ICCAD-2011), San Jose, CA, Nov. 2011, pp. 742—746, San Jose, CA
2011 Hua-Yu Chang, Iris Hui-Ru Jiang, and Yao-Wen Chang, Simultaneous functional and timing ECO, Proc. 48th ACM/IEEE Design Automation Conference (DAC-2011), San Diego, CA, June 2011, pp. 140—145, San Diego, CA
2011 Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, and Lancer S.-F. Chen, INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs, Proc. 20th ACM International Symposium on Physical Design (ISPD-2011), Santa Barbara, CA, Mar. 2011, pp. 115—121, Santa Barbara, CA
2011 Cheng-Chi Chan, Yen-Ting Yu, and Iris Hui-Ru Jiang, 3DICE: 3D IC cost evaluation based on fast tier number estimation, Proc. 12th IEEE International Symposium on Quality Electronic Design (ISQED-2011), Santa Clara, CA, Mar. 2011, pp. 50—55, Santa Clara, CA
2011 Chuan-Yao Tan and Iris Hui-Ru Jiang, Recent research development in metal-only ECO, Proc. 54th IEEE Midwest Symposium on Circuits and Systems (MWSCAS-2011), Seoul, Korea, Aug. 2011, pp. 1—4, Seoul, Korea
2011 Hua-Yu Chang, Yao-Wen Chang, and Iris Hui-Ru Jiang, Cost-effective timing ECO optimization, 22nd VLSI Design/CAD Symposium, Yulin, Taiwan, Aug. 2011, Yulin, Taiwan
2010 Houng-Yi Li, Iris Hui-Ru Jiang, and Hung-Ming Chen, Simultaneous voltage island generation and floorplanning, Proc. 23rd IEEE International SOC Conference (SOCC-2010), Las Vegas, CA, Sep. 2010, pp. 219—223, Las Vegas, CA
2010 Iris Hui-Ru Jiang and Hua-Yu Chang, ECOS: A metal-only ECO synthesizer, IEEE International Symposium on Circuits and Systems (ISCAS-2010), Paris, France, May 2010, p. 2774, Paris, France
2010 Yu-Ming Yang and Iris Hui-Ru Jiang, Analog placement and global routing considering wiring symmetry, Proc. 11th IEEE International Symposium on Quality Electronic Design (ISQED-2010), San Jose, CA, Mar. 2010, pp. 618—623, San Jose, CA
2010 Iris Hui-Ru Jiang, Hua-Yu Chang, and Chih-Long Chang, Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles, Proc. 19th ACM International Symposium on Physical Design (ISPD-2010), San Francisco, CA, Mar. 2010, pp. 177—184, San Francisco, CA
2010 Yu-Ming Yang and Iris Hui-Ru Jiang, Analog layout generation based on wiring symmetry, 16th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2010), Taipei, Taiwan, Oct. 2010, Taipei, Taiwan
2010 Iris Hui-Ru Jiang, Hua-Yu Chang, and Chih-Long Chang, Optimal wiring topology for electromigration avoidance, 16th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2010), Taipei, Taiwan, Oct. 2010, Taipei, Taiwan
2010 Yu-Ming Yang and Iris Hui-Ru Jiang, Analog layout generation based on wiring symmetry, 21st VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010, Kaohsiung, Taiwan
2009 Iris Hui-Ru Jiang, Generic integer linear programming formulation for 3D IC partitioning, Proc. 22nd IEEE International SOC Conference (SOCC-2009), Belfast, Northern Ireland, UK, Sep. 2009, pp. 321—324, Belfast, Northern Ireland, UK
2009 Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, and Huang-Bi Hung, Matching-based minimum-cost spare cell selection for design changes, Proc. 46th ACM/IEEE Design Automation Conference (DAC- 2009), San Francisco, CA, Jul. 2009, pp. 408—411, San Francisco, CA
2009 Iris Hui-Ru Jiang and Ming-Hua Wu, POSA: power-state-aware buffered tree construction, IEEE International Symposium on Circuits and Systems (ISCAS-2009), Taipei, Taiwan, May 2009, p. 787, Taipei, Taiwan
2009 Wan-Yu Lee and Iris Hui-Ru Jiang, VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power, Proc. 19th ACM Great Lakes Symposium on VLSI (GLSVLSI-2009), Boston, Massachusetts, May 2009, pp. 39—44, Boston, Massachusetts
2009 Chih-Long Chang and Iris Hui-Ru Jiang, A provably good algorithm for electromigration-avoidance rectilinear Steiner trees, 20th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2009
2009 Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, and Huang-Bi Hung, Matching-based spare cell selection for design changes, 20th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2009, Hualien, Taiwan
2009 Wan-Yu Lee and Iris Hui-Ru Jiang, Variability tolerance on throughput and power for 3D chipmultiprocessors, 18th International Workshop on Logic & Synthesis (IWLS-2009), Berkeley, CA, Jul. 2009, Berkeley, CA
2009 Wan-Yu Lee and Iris Hui-Ru Jiang, Variability characterization and tolerance on throughput and power for chip-multiprocessors, 15th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2009), Okinawa, Japan, Mar. 2009, Okinawa, Japan
2008 Iris Hui-Ru Jiang and Ming-Hua Wu, Power-state-aware buffered tree construction, Proc. 26th IEEE International Conference on Computer Design (ICCD-2008), Lake Tahoe, CA, Oct. 2008, pp. 21—26, Lake Tahoe, CA
2008 Iris Hui-Ru Jiang and Yen-Ting Yu, Configurable rectilinear Steiner tree construction for SoC and nano technologies, Proc. 26th IEEE International Conference on Computer Design (ICCD-2008), Lake Tahoe, CA, Oct. 2008, pp. 34—39, Lake Tahoe, CA
2008 Iris Hui-Ru Jiang, Shung-Wei Lin, and Yen-Ting Yu, Unification of obstacle-avoiding rectilinear Steiner tree construction, Proc. 21st IEEE International SOC Conference (SOCC-2008), Newport Beach, CA, Sep. 2008, pp. 127—130, Newport Beach, CA
2008 Wan-Yu Lee and Iris Hui-Ru Jiang, Topology generation and floorplanning for low power applicationspecific network-on-chips, Proc. 4th IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2008), Hsinchu, Taiwan, Apr. 2008, pp. 283—286, Hsinchu, Taiwan
2008 Yen-Ting Yu and Iris Hui-Ru Jiang, Obstacle-avoiding preferred direction rectilinear Steiner tree construction for SoC and nano technologies, 19th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2008, Kenting, Taiwan
2008 Shung-Wei Lin, Iris Hui-Ru Jiang, and Yen-Ting Yu, Unified obstacle-avoiding rectilinear Steiner tree construction, 19th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2008, Kenting, Taiwan
2007 Wan-Yu Lee and Iris Hui-Ru Jiang, Topology generation and floorplanning for low power applicationspecific network-on-chips, 14th Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2007), Sapporo, Hokkaido, Japan, Oct. 2007, Sapporo, Hokkaido, Japan
2007 Ming-Hua Wu and Iris Hui-Ru Jiang, On power-state-aware routing and buffer insertion, 18th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2007, Hualien, Taiwan
2007 Wan-Yu Lee and Iris Hui-Ru Jiang, Topology generation and floorplanning for low power applicationspecific network-on-chips, 18th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2007, Hualien, Taiwan
2006 Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, and Hui-Ru Jiang, “Performance constraints aware voltage islands generation in SoC floorplan design, Proc. 19th IEEE International SOC Conference (SOCC- 2006), Austin, Texas, Sep. 2006, pp. 211—214, Austin, Texas
2003 Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, and Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proc. ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC- 2003), Kitakyushu, Japan, Jan. 2003, pp. 431—434, Kitakyushu, Japan
2002 Nicholas Chia-Yuan Chang, Yao-Wen Chang, and Iris Hui-Ru Jiang, Formulate for performance optimization and their applications to interconnect-driven floorplannin, Proc. 3rd IEEE International Symposium on Quality Electronic Design (ISQED-2002), San Jose, CA, Mar. 2002, pp. 523—528, San Jose, CA
2001 Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, and Tai-Sheng Feng, On placement and routing of wafer scale memory, Proc. 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS-2001), Malta, Sep. 2001, pp. 883—887, vol. 2, Malta
2001 Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, and Tai-Sheng Feng, On integration for wafer scale memory, 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001, Hsinchu, Taiwan
2000 Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, and Jing-Yang Jou, Optimal reliable crosstalk-driven interconnect optimization, Proc. 9th ACM International Symposium on Physical Design (ISPD-2000), San Diego, CA, Apr. 2000, pp. 128—133, San Diego, CA
2000 Chia-Yuan Chang, Yao-Wen Chang, and Iris Hui-Ru Jiang, Simultaneous buffer-insertion/-sizing and wiresizing formulae with applications to interconnect-driven floorplanning, 11th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2000, Pingdong, Taiwan
1999 Jie-Hong R. Jiang and Iris Hui-Ru Jiang, Optimum loading dispersion for high-speed tree-type decision circuitry, Proc. 17th IEEE/ACM International Conference on Computer Aided Design (ICCAD-1999), San Jose, CA, Nov. 1999, pp. 520—524, San Jose, CA
1999 Mango C.-T. Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, and Yao-Wen Chang, A clustering- and probabilitybased approach for time-multiplexed FPGAs partitioning, Proc. 17th IEEE/ACM International Conference on Computer Aided Design (ICCAD-1999), San Jose, CA, Nov. 1999, pp. 364—368, San Jose, CA
1999 Hui-Ru Jiang, Jing-Yang Jou, and Yao-Wen Chang, Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation, Proc. 36th ACM/IEEE Design Automation Conference (DAC-1999), New Orleans, LA, Jun. 1999, pp. 90—95, New Orleans, LA
1999 Jiann-Horng Lin, Jing-Yang Jou, and Hui-Ru Jiang, Hierarchical floorplan design on the internet, Proc. 4th ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-1999), Hong Kong, Jan. 1999, pp. 189—192, Hong Kong
1999 Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, and Jing-Yang Jou, Reliable crosstalk-driven interconnect optimization in the deep submicron technology, 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999, Nangtou, Taiwan
專利名稱 專利編號 專利國別 作者
“DRC-based hotspot detection considering edge tolerance and incomplete specification US Yen-Ting Yu, Hui-Ru Jiang, Yumin Zhang, and Charles C. Chiang
工程變更之保持時間修復方法 Taiwan Hui-Ru Jiang, Yu-Ming Yang, and Sung-Ting Ho
時序設計變更的方法 Taiwan Hua-Yu Chang, Hui-Ru Jiang, and Yao-Wen Chang
Engineering change order hold time fixing method US Hui-Ru Jiang, Yu-Ming Yang, and Sung-Ting Ho
Method of implementing timing engineering change order US Hua-Yu Chang, Hui-Ru Jiang, and Yao-Wen Chang
Method for designing wiring topology 連線拓樸設計 方法 Taiwan Hui-Ru Jiang, Hua-Yu Chang, and Chih-Long Chang
Lithographic hotspot detection using multiple machine learning kernels US Charles C. Chiang, Yen-Ting Yu, Geng-He Lin, and Hui-Ru Jiang
Accurate processhotspot detection using critical design rule extraction US Charles C. Chiang, Yen-Ting Yu, Hui-Ru Jiang, Subarnarekha Sinha, and Ya-Chung Chan
“Designing an optimal wiring topology for electromigration avoidance US Hui-Ru Jiang, Hua-Yu Chang, and Chih-Long Chang
考量元件與佈線對稱之類比佈局方法 Taiwan Yu-Ming Yang and Hui-Ru Jiang
“Method for analog placement and global routing considering wiring symmetry US Hui-Ru Jiang and Yu-Ming Yang
Method and related apparatus for performing error checkingcorrecting US Jiing Lin, Hui-Ru Jiang, and Jie Ding
Method and related apparatus for data error checking US Jiing Lin, Hui-Ru Jiang, and Jie Ding
國家 學校名稱 系所 學位
台灣 國立交通大學 電子工程 博士
台灣 國立交通大學 電子工程 學士
服務機關名稱 單位 職務
國立交通大學 國際半導體產業學院 合聘教授
至達科技 顧問
國立交通大學 電子工程學系所 教授
IBM 奧斯汀研究實驗室 訪問學者
國立交通大學 電子工程學系所 副教授
工研院 SoC技術中心 顧問
國立交通大學 電子工程學系所 助理教授
威盛科技有限公司 高級工程師
國立交通大學 電子工程學系 研究助理
國立交通大學 電子工程學系 助教
2016 Best Paper Nominee, ACM/EDAC/IEEE Design Automation Conf. (DAC)
2015 Certificate of Appreciation, IEEE Council on Electronic Design Automation (CEDA)
2015 NCTU Research Award
2015 1st Place Award, 2015 ACM TAU Timing Analysis Contest (Students: Pei-Yu Lee, et al.)
2014 3rd Place Award, 2014 ACM TAU Timing Analysis Contest (Students: Yu-Ming Yang and Yu-Wei Chang)
2014 Best-in-Track Paper, 2014 IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD)
2013 3rd Place Award, 2013 ACM TAU Timing Analysis Contest (Students: Yu-Ming Yang et al.)
2013 Best Paper Nominee, ACM Int’l Symp. on Physical Design (ISPD)
2013 Visiting Scholarship, National Science Council, Taiwan
2012 Excellent Young Researcher Project Award, National Science Council, Taiwan
2012 NCTU Research Award
2012 1st Place Award, 2012 CAD Contest at ICCAD (Students: Yen-Ting Yu and Geng-He Lin)
2011 中國電機工程學會優秀青年電機工程師獎
2011 Best Paper Nominee, 22th VLSI Design/CAD Symp.
2010 The Best Tool Award, Taiwan Ministry of Education U-Tools Forum
2009 EDA Scholarship, Springsoft Foundation
2009 NCTU Outstanding Mentor Award
2009 Who’s Who in the World, 2009 edition
2010 Who’s Who in Science and Engineering, 2011-2012
2003 中華民國斐陶斐榮譽學會榮譽會員
2000 The Best Student Paper Award, 11th VLSI Design/CAD Symp.
1997--99 Fellowship, Ministry of Education, Taiwan (1st place, Ph.D. program)
1997 Fellowship, Ministry of Education, Taiwan (1st place, MS program)
1998 Scholarship, Pan Wen Yuan Foundation
1998 Mr. Chia-Yu Yang’s Memorial Scholarship
1997--98 Scholarship, Rotary Foundation
1996--97 Academic Achievement Award (1st place, Inst. of Electronics, National Chiao Tung Univ.)
1995 Undergraduate Research and Development Award, National Science Council, Taiwan
1995 Outstanding Award, Taiwan Ministry of Education Software Development Contest
1995 Bronze Prize, Undergraduate Research and Development Award, NCTU
1995 Mr. Chi-Tung Yin’s Undergraduate Research and Development Award, NCTU